img_txt.m
clear all close all clc img1 = imread('sobel.jpg'); img2 = imread('sobel.jpg'); img3 = imread('sobel.jpg'); img4 = imread('sobel.jpg'); img5 = imread('sobel.jpg'); R1=img1(:,:,1); G1=img1(:,:,2); B1=img1(:,:,3); R2=img2(:,:,1); G2=img2(:,:,2); B2=img2(:,:,3); R3=img3(:,:,1); G3=img3(:,:,2); B3=img3(:,:,3); R4=img4(:,:,1); G4=img4(:,:,2); B4=img4(:,:,3); R5=img5(:,:,1); G5=img5(:,:,2); B5=img5(:,:,3); %************************** [a,b,c]= size(img1); fidR1= fopen('R_frame1.txt','w'); fidG1= fopen('G_frame1.txt','w'); fidB1= fopen('B_frame1.txt','w'); fidR2= fopen('R_frame2.txt','w'); fidG2= fopen('G_frame2.txt','w'); fidB2= fopen('B_frame2.txt','w'); fidR3= fopen('R_frame3.txt','w'); fidG3= fopen('G_frame3.txt','w'); fidB3= fopen('B_frame3.txt','w'); fidR4= fopen('R_frame4.txt','w'); fidG4= fopen('G_frame4.txt','w'); fidB4= fopen('B_frame4.txt','w'); fidR5= fopen('R_frame5.txt','w'); fidG5= fopen('G_frame5.txt','w'); fidB5= fopen('B_frame5.txt','w'); for i=1:a for j= 1:b fprintf(fidR1,'%d\n',R1(i,j)); %frame1 fprintf(fidG1,'%d\n',G1(i,j)); fprintf(fidB1,'%d\n',B1(i,j)); fprintf(fidR2,'%d\n',R2(i,j)); %frame2 fprintf(fidG2,'%d\n',G2(i,j)); fprintf(fidB2,'%d\n',B2(i,j)); fprintf(fidR3,'%d\n',R3(i,j)); %frame3 fprintf(fidG3,'%d\n',G3(i,j)); fprintf(fidB3,'%d\n',B3(i,j)); fprintf(fidR4,'%d\n',R4(i,j)); %frame4 fprintf(fidG4,'%d\n',G4(i,j)); fprintf(fidB4,'%d\n',B4(i,j)); fprintf(fidR5,'%d\n',R5(i,j)); %frame5 fprintf(fidG5,'%d\n',G5(i,j)); fprintf(fidB5,'%d\n',B5(i,j)); end end fclose(fidR1); fclose(fidG1); fclose(fidB1); fclose(fidR2); fclose(fidG2); fclose(fidB2); fclose(fidR3); fclose(fidG3); fclose(fidB3); fclose(fidR4); fclose(fidG4); fclose(fidB4); fclose(fidR5); fclose(fidG5); fclose(fidB5); figure, subplot(331),imshow(img1),title('img1'); subplot(332),imshow(img2),title('img2'); subplot(333),imshow(img3),title('img3'); subplot(334),imshow(img4),title('img4'); subplot(335),imshow(img5),title('img5');
txt_img.m
clear all close all clc img = imread('sobel.jpg'); [a,b,c]= size(img); img2R = uint8(textread('Result_Frame1_R.txt','%u')); img2G = uint8(textread('Result_Frame1_G.txt','%u')); img2B = uint8(textread('Result_Frame1_B.txt','%u')); img3R = uint8(textread('Result_Frame2_R.txt','%u')); img3G = uint8(textread('Result_Frame2_G.txt','%u')); img3B = uint8(textread('Result_Frame2_B.txt','%u')); img4R = uint8(textread('Result_Frame3_R.txt','%u')); img4G = uint8(textread('Result_Frame3_G.txt','%u')); img4B = uint8(textread('Result_Frame3_B.txt','%u')); img5R = uint8(textread('Result_Frame4_R.txt','%u')); img5G = uint8(textread('Result_Frame4_G.txt','%u')); img5B = uint8(textread('Result_Frame4_B.txt','%u')); img6R = uint8(textread('Result_Frame5_R.txt','%u')); img6G = uint8(textread('Result_Frame5_G.txt','%u')); img6B = uint8(textread('Result_Frame5_B.txt','%u')); img2(:,:,1) = reshape(img2R,[b,a]); img2(:,:,2) = reshape(img2G,[b,a]); img2(:,:,3) = reshape(img2B,[b,a]); img3(:,:,1) = reshape(img3R,[b,a]); img3(:,:,2) = reshape(img3G,[b,a]); img3(:,:,3) = reshape(img3B,[b,a]); img4(:,:,1) = reshape(img4R,[b,a]); img4(:,:,2) = reshape(img4G,[b,a]); img4(:,:,3) = reshape(img4B,[b,a]); img5(:,:,1) = reshape(img5R,[b,a]); img5(:,:,2) = reshape(img5G,[b,a]); img5(:,:,3) = reshape(img5B,[b,a]); img6(:,:,1) = reshape(img6R,[b,a]); img6(:,:,2) = reshape(img6G,[b,a]); img6(:,:,3) = reshape(img6B,[b,a]); figure, subplot(331),imshow(img),title('img'); subplot(332),imshow(fliplr(imrotate(img2,-90))),title('img2'); subplot(333),imshow(fliplr(imrotate(img3,-90))),title('img3'); subplot(334),imshow(fliplr(imrotate(img4,-90))),title('img4'); subplot(335),imshow(fliplr(imrotate(img5,-90))),title('img5'); subplot(336),imshow(fliplr(imrotate(img6,-90))),title('img6'); figure,imshow(fliplr(imrotate(img6,-90))),title('img6');
sobel.jpg[图片]
FPGA 的verilog源码如下
vga_parameter.vhvga_ctl.vtb_image.vSobel.vrgb2ycbcr.vlinebuffer.vline.vimwrite_frame5.vimwrite_frame4.vimwrite_frame3.vimwrite_frame2.vimread_frame1.vfifo_linebuffer.v
[图片]
Analysis and Synthesis should be completed successfully beforestarting RTL NativeLink Simulation
问题原因仿真前需要在Quartus II中执行一次分析和综合。
解决方法仿真前需要在Quartus II中执行一次分析和综合。 [图片]
你的LP管脚约束是错的,应该用LVCMOS12,也就是1.2V的IO。我看你有的是1.2有的是2.5很混乱。
边界有没有注意啊?一次读写不能跨32burst不能跨行操作就是说连读的过程不要跨行,因为跨行要切换行地址。这个是需要操作时间的。
模块没展开:1.要么是你这个模块的文件没有添加进来2.要么是你用的NGO文件没有添加到库的搜索路径中,如果是这个问题参见下面这个链接https://chipdebug.com/forum-post/55.html3.该装的IP没有安装。参见 https://chipdebug.com/forum-post/236.html
问题2,3:2.如果读到的DEVICE_ID不对,说明你的MCU程序有问题,PC软件的DEVICE_ID是没有问题,在进行所有其它操作前,先把这一步调通,它是验证通信的基石,不知道你的代码是哪来的,这个链接里有一个其它客户调通的示例代码。https://chipdebug.com/forum-post/61.html/
3.生成你所说文件的操作步骤在上面的链接里有。https://chipdebug.com/forum-post/43.html
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img_txt.m
txt_img.m
sobel.jpg
[图片]
FPGA 的verilog源码如下
vga_parameter.vh
vga_ctl.v
tb_image.v
Sobel.v
rgb2ycbcr.v
linebuffer.v
line.v
imwrite_frame5.v
imwrite_frame4.v
imwrite_frame3.v
imwrite_frame2.v
imread_frame1.v
fifo_linebuffer.v