lattice fpga crosslink怎样使用内嵌的reveal analyzer逻辑分析仪？-Lattice-莱迪斯社区-FPGA CPLD-ChipDebug

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- ii13970
  1. Crosslink Reveal 使用是通过共享SPI管脚,连接方式如下:
    USB CABLE++++++++CROSSLINK
    
    TDI—————->MOSI，
    TDO—————>MISO,
    TMS—————>SPI_SS/CSN,
    ispEN/PROG—-> SPI_SS/CSN ,
  2. JTAG模式下链接TMS脚到SPI_SS/CSN，加载的时候ispEN/PROG链接到SPI_SS/CSN。TCK需要采用PCLK(此处用SPI加载的SPI_CLK/MCLK来替代，但要加约束)实现。也就是说SPI加载和使用JTAG的reveal是可以共享的，只是差了一个脚SPI_SS/CSN需要在两个情况下切换。同时需要把Spreadsheet==>Global Preferences==>SysConfig==>SLAVE SPI 给disable掉。才可以正常使用reveal。
  3. 在使用reveal的时候需要detect cable此时要把CRESETB拿掉，不能连接，否则会让已经加载在SDRAM的程序丢失。
  4. 在par command里设置“-exp WARNING_ON_PCLKPLC1=1”，否则会因为TCK没有走PCLK而导致布线错误。
  6年前回复
- 52fpga0
  上传一份在官方DEMO板(CrossLink: LIF-MD6000 – Master Link Board)上使用Reveal的文档，供参考。
  
  How to run Reveal Soft JTAG Debugger on SNOW Master Link Board Rev-A
  
  1.Install Diamond 3.7 + SNOW (LIFMD) Control Pack
  
  2.Modify SNOW Master Link Board Rev-A
  • According to schematic, Reveal soft jtag need to use J5 connector IO
  • But J5 connector IO also connected to 4 blue leds D{6,7,8,9}
  • Need to disconnect resistors R{54,55,57,59} from CMOSIO{1,2,3,4}
  • Unsolder 4 resistors R{54,55,57,59} from the board shown below
  
  3.Connect SNOW Master Link Board Rev-A to PC
  • Connect USB2 cable to mini connector for download bitstream (FTUSB-0)
  • Connect USBN-2A cable to J5 connector for soft jtag debug (EzUSB-0)
  o JTAG_TDI (orange wire)=> E7 (J5-pin1)
  o JTAG_TCK (white wire)=> F7 (J5-pin2)
  o JTAG_TMS (purple wire)=> G8 (J5-pin3)
  o JTAG_TDO (brown wire)=> H7 (J5-pin4)
  o VDD (red wire) => VCC (J18-pin1)
  o GND (black wire) => GND (J18-pin10)
  
  4.Control rstn signal of design using connector J6-pin2 (G9=high when open)
  
  LOCATE COMP “rstn” SITE “G9” ;
  LOCATE COMP “JTAG_TDI” SITE “E7” ;
  LOCATE COMP “JTAG_TCK” SITE “F7” ;
  LOCATE COMP “JTAG_TMS” SITE “G8” ;
  LOCATE COMP “JTAG_TDO” SITE “H7” ;
  1. Use internal oscillator OSCI to provide sample clock for the design
```
module count(c,rstn);
input rstn; 
output [24:0]c; 
reg [24:0]c;
OSCI osc_inst ( .HFOUTEN(1'b1),  .HFCLKOUT(osc_clk),  .LFCLKOUT());
defparam osc_inst.HFCLKDIV = 2;
always @(posedge osc_clk or negedge rstn)
     begin
if (~rstn)
  c = 24'b0;
    else
        c = c + 1;
      end 
endmodule
```
  6.Placement engine will select JTAG_TCK as a primary clock and expect “F7” having Type=PCLKT* to drive PCLK tree, otherwise DRC will report violation. Need to avoid DRC error with this option in PAR Strategy: “-exp WARNING_ON_PCLKPLC1=1”
  
  7.Generate and download bitstream to board on FTUSB-0
  
  8.Run Reveal Analyzer on EzUSB-0 (do not click Scan when create new rva)
  6年前回复

lattice fpga crosslink怎样使用内嵌的reveal analyzer逻辑分析仪？

How to run Reveal Soft JTAG Debugger on SNOW Master Link Board Rev-A