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速率要求这个器件手册上有个表。
如果是差分，输出只有左右bank的A/B支持，输入左右bank的A/B,C/D都支持，上下bank不支持lvds
带有PCLK的都是全局时钟。
单端输入只能是A，剩下的B可以当普通io用
如果你输出时钟是单端的，任何管脚都可以。差分还是用lvds 输出规则，Lvds 输出只能用2.5v的vccio。