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不够的话,只能用数据居中的,而且沿对齐的必须大于100mhz,做多4个dll。发送用沿对齐,接收用居中,接收时钟必须用pclkt。
就ecp5来说,接收,沿对齐,每组需要dll移相90度;居中,不需要dll,也不需要pll.发送,沿对齐,不需要pll,dll;居中需要用pll移相90度
这些都不是内存条的ddr接口为何有这种限制? 我们之前用altera和Xilinx没发现这种普通的iDDR,oddr接口需要pll资源的问题。 为何lattice需要呢?