7.1i XST  – “错误:Xst:792  – ”  .v“第8行:索引7不在信号范围内为单位设置属性“resynthesize = true”  “-Altera-Intel社区-FPGA CPLD-ChipDebug

7.1i XST – “错误:Xst:792 – ” .v“第8行:索引7不在信号范围内