LogiCORE SPI-4.2 Lite(POS-PHY L4)v2.0  –  RTL仿真生成错误:“时序违规错误:实例上的FINE_SHIFT_RANGE超过10.000 ns.PHASE_SHIFT * PERIOD / 256 = -255”-Altera-Intel社区-FPGA CPLD-ChipDebug