LATTICE EPC3 DDR3管脚约束给与BANK冲突-Altera-Intel社区-FPGA CPLD-ChipDebug

LATTICE EPC3 DDR3管脚约束给与BANK冲突

Cryingcat徽章-元老玩家-ChipDebug等级-LV2-ChipDebug6年前发布
2883

大家好，我在使用LATTCIE ECP3器件进行DDR3设计时，发现工程可以成功编译，但是当打开spreadsheet后就会报下面的错误，下面这三个脚，我无论改为BANK6、BANK7中的任何一个管脚都会显示

Bank setting conflicts with the bank of ‘’ : 6
LATTICE EPC3 DDR3管脚约束冲突.png

但是当我把这个管脚换到BANK0时就可以了。另外如果我把这些管脚清理掉，让工具自己跑，它又会将这些管脚放到BANK6，只是打开spread sheet一直会出错，折腾了几天了也没解决，请大伙帮忙看看。

下面是我的LPF约束文件：

RVL_ALIAS "sclk" "u_ddr_ulogic/sclk"; 
RVL_ALIAS "sclk" "u_ddr_ulogic/sclk"; 
RVL_ALIAS "sclk" "u_ddr_ulogic/sclk"; 
RVL_ALIAS "sclk" "u_ddr_ulogic/sclk"; 
RVL_ALIAS "sclk" "u_ddr_ulogic/sclk"; 
RVL_ALIAS "sclk" "u_ddr_ulogic/sclk"; 
RVL_ALIAS "sclk" "u_ddr_ulogic/sclk"; 
COMMERCIAL ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
##########################################################################
# Frequency Declerations
##########################################################################
FREQUENCY NET "clk_in_c" 100.000000 MHz ;
FREQUENCY NET "sclk" 200.000000 MHz PAR_ADJ 40.000000 ;
FREQUENCY NET "u_ddr3_sdram_mem_top/clkos" 400.000000 MHz PAR_ADJ 80.000000 ;
USE PRIMARY NET "clk_in_c" ;
USE PRIMARY NET "sclk" ;
USE PRIMARY NET "clkos" ;
USE PRIMARY NET "sclk2x" ;
##########################################################################
# Block, Maxdelay, Multicycle preferences
##########################################################################
BLOCK PATH FROM PORT "reset_*" ;
BLOCK NET "*read_pulse_tap*" ;
MAXDELAY NET "*/U1_ddr3_sdram_phy/ddr3_read_data_out*" 4.500000 ns ;
MAXDELAY NET "*/U1_ddr3_sdram_phy/datavalid_o[*]" 4.400000 ns ;
MULTICYCLE FROM CELL "*/uddcntln" 2.000000 X ;
#Half SCLK clock path
MAXDELAY TO CELL "*/dq_read_o_n0*" 5.000000 ns ;
#sclk(-)  or sclk(+) to sclk2x(+)
MAXDELAY TO CELL "*/dq_read_o_t2_sclk*" 2.500000 ns ;
#Half SCLK2x clock path
MAXDELAY TO CELL "*/dq_read_o_n00*" 2.500000 ns ;
#Mux input and output paths
MAXDELAY NET "*/dq_read_o_p01*" 0.550000 ns ;
MAXDELAY NET "*/dq_read_o_n00*" 0.550000 ns ;
MAXDELAY NET "*/dqs_read*" 0.615000 ns ;
##########################################################################
# CSM logic preferences
##########################################################################
BLOCK PATH FROM CLKNET "clk_in_c" TO CLKNET "sclk" ;
BLOCK PATH FROM CLKNET "clk_in_c" TO CLKNET "u_ddr3_sdram_mem_top/clkos" ;
BLOCK PATH FROM CLKNET "sclk" TO CLKNET "clk_in_c" ;
BLOCK PATH FROM CLKNET "*sclk2x" TO CLKNET "clk_in_c" ;
BLOCK PATH FROM CLKNET "clk_in_c" TO CLKNET "*eclk" ;
BLOCK PATH FROM CLKNET "u_ddr3_sdram_mem_top/clkos" TO CLKNET "*eclk" ;
BLOCK PATH FROM CLKNET "u_ddr3_sdram_mem_top/clkos" TO CLKNET "sclk" ;
BLOCK PATH FROM CLKNET "*sclk2x" TO CLKNET "u_ddr3_sdram_mem_top/clkos" ;
MAXDELAY NET "*pll_phase*" 2.500000 ns ;
MAXDELAY NET "*dqclk1bar_ff" 0.650000 ns ;
MAXDELAY NET "*eclk" 1.200000 ns ;
MAXDELAY NET "*U1_clocking/stop" 0.800000 ns ;
MAXDELAY NET "u_ddr3_sdram_mem_top/clkos" 1.100000 ns ;
##########################################################################
# IO Type Declarations
##########################################################################
IOBUF ALLPORTS IO_TYPE=LVCMOS15 ;
DEFINE PORT GROUP "EM_DDR_DQS_GRP" "em_ddr_dqs*" ;
IOBUF GROUP "EM_DDR_DQS_GRP" IO_TYPE=SSTL15D EQ_CAL=0 DRIVE=8 ;
DEFINE PORT GROUP "EM_DDR_DATA_GRP" "em_ddr_data*" ;
IOBUF GROUP "EM_DDR_DATA_GRP" IO_TYPE=SSTL15 DRIVE=8 ;
DEFINE PORT GROUP "EM_DDR_DM_GRP" "em_ddr_dm[*]" ;
IOBUF GROUP "EM_DDR_DM_GRP" IO_TYPE=SSTL15 DRIVE=8 ;
DEFINE PORT GROUP "EM_DDR_ADDR_GRP" "em_ddr_addr[*]" ;
IOBUF GROUP "EM_DDR_ADDR_GRP" IO_TYPE=SSTL15 BANK=0 DRIVE=8 ;
DEFINE PORT GROUP "EM_DDR_BA_GRP" "em_ddr_ba[*]" ;
IOBUF GROUP "EM_DDR_BA_GRP" IO_TYPE=SSTL15 BANK=0 DRIVE=8 ;
IOBUF PORT "em_ddr_ras_n" IO_TYPE=SSTL15 DRIVE=8 TERMINATEVTT=OFF PULLMODE=NONE SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_cas_n" IO_TYPE=SSTL15 DRIVE=8 TERMINATEVTT=OFF PULLMODE=NONE SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_we_n" IO_TYPE=SSTL15 DRIVE=8 TERMINATEVTT=OFF PULLMODE=NONE SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
DEFINE PORT GROUP "EM_DDR_CS_GRP" "em_ddr_cs_n[*]" ;
IOBUF GROUP "EM_DDR_CS_GRP" IO_TYPE=SSTL15 BANK=0 DRIVE=8 ;
DEFINE PORT GROUP "EM_DDR_ODT_GRP" "em_ddr_odt[*]" ;
IOBUF GROUP "EM_DDR_ODT_GRP" IO_TYPE=SSTL15 BANK=0 DRIVE=8 ;
DEFINE PORT GROUP "EM_DDR_CKE_GRP" "em_ddr_cke[*]" ;
IOBUF GROUP "EM_DDR_CKE_GRP" IO_TYPE=SSTL15 BANK=0 DRIVE=8 ;
DEFINE PORT GROUP "EM_DDR_CLK_GRP" "em_ddr_clk[*]" ;
IOBUF GROUP "EM_DDR_CLK_GRP" IO_TYPE=SSTL15D BANK=6 DRIVE=10 ;
IOBUF PORT "clk_in" IO_TYPE=SSTL15D PULLMODE=NONE DIFFRESISTOR=OFF ;
IOBUF PORT "em_ddr_reset_n" IO_TYPE=LVCMOS15 TERMINATEVTT=OFF PULLMODE=UP DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
##########################################################################
## LOCATE FOR CSM logic
##########################################################################
LOCATE COMP "clk_in" SITE "L5" ;
LOCATE COMP "u_ddr3_sdram_mem_top/U1_ddr3_pll/PLLInst_0" SITE "PLL_R35C5" ;
LOCATE COMP "u_ddr3_sdram_mem_top/U1_clocking/sync" SITE "LECLKSYNC2" ;
LOCATE PGROUP "u_ddr3_sdram_mem_top/U1_clocking/clk_phase/phase_ff_0_inst/clk_phase0" SITE "R24C5D" ;
LOCATE PGROUP "u_ddr3_sdram_mem_top/U1_clocking/clk_phase/dqclk1bar_ff_inst/clk_phase1a" SITE "R34C2D" ;
LOCATE PGROUP "u_ddr3_sdram_mem_top/U1_clocking/clk_phase/phase_ff_1_inst/clk_phase1b" SITE "R34C2D" ;
LOCATE PGROUP "u_ddr3_sdram_mem_top/U1_clocking/clk_stop/clk_stop" SITE "R34C2D" ;
##########################################################################
### DIMM ADDR/CMD/CTRL/CLK
##########################################################################
# LOCATE COMP "em_ddr_addr[0]"  SITE "C8" ;
# LOCATE COMP "em_ddr_addr[1]"  SITE "C7" ;
# LOCATE COMP "em_ddr_addr[2]"  SITE "B7" ;
# LOCATE COMP "em_ddr_addr[3]"  SITE "D8" ;
# LOCATE COMP "em_ddr_addr[4]"  SITE "F9" ;
# LOCATE COMP "em_ddr_addr[5]"  SITE "E9" ;
# LOCATE COMP "em_ddr_addr[6]"  SITE "A3" ;
# LOCATE COMP "em_ddr_addr[7]"  SITE "D7" ;
# LOCATE COMP "em_ddr_addr[8]"  SITE "A7" ;
# LOCATE COMP "em_ddr_addr[9]"  SITE "B8" ;
# LOCATE COMP "em_ddr_addr[10]" SITE "C9" ;
# LOCATE COMP "em_ddr_addr[11]" SITE "C10" ;
# LOCATE COMP "em_ddr_addr[12]" SITE "F7" ;
# LOCATE COMP "em_ddr_clk[0]"   SITE "K4" ;
# LOCATE COMP "em_ddr_cke[0]"   SITE "G8" ;
# LOCATE COMP "em_ddr_ba[0]"    SITE "B4" ;
# LOCATE COMP "em_ddr_ba[1]"    SITE "E6" ;
# LOCATE COMP "em_ddr_ba[2]"    SITE "D5" ;
# LOCATE COMP "em_ddr_ras_n"   SITE "A6" ;
# LOCATE COMP "em_ddr_cas_n"   SITE "A4" ;
# LOCATE COMP "em_ddr_we_n"    SITE "D6" ;
# LOCATE COMP "em_ddr_cs_n[0]"  SITE "C6" ;
# LOCATE COMP "em_ddr_odt[0]"   SITE "E7" ;
# LOCATE COMP "em_ddr_reset_n" SITE "D4" ;
##########################################################################
# DIMM DQ, DQS, DM
##########################################################################
# LOCATE COMP "em_ddr_data[0]"  SITE "E5" ;
# LOCATE COMP "em_ddr_data[1]"  SITE "E4" ;
# LOCATE COMP "em_ddr_data[2]"  SITE "D2" ;
# LOCATE COMP "em_ddr_data[3]"  SITE "D1" ;
# LOCATE COMP "em_ddr_data[4]"  SITE "C2" ;
# LOCATE COMP "em_ddr_data[5]"  SITE "B2" ;
# LOCATE COMP "em_ddr_data[6]"  SITE "G5" ;
# LOCATE COMP "em_ddr_data[7]"  SITE "G4" ;
# LOCATE COMP "em_ddr_data[8]"  SITE "G2" ;
# LOCATE COMP "em_ddr_data[9]"  SITE "F1" ;
# LOCATE COMP "em_ddr_data[10]" SITE "H4" ;
# LOCATE COMP "em_ddr_data[11]" SITE "E2" ;
# LOCATE COMP "em_ddr_data[12]" SITE "J4" ;
# LOCATE COMP "em_ddr_data[13]" SITE "B1" ;
# LOCATE COMP "em_ddr_data[14]" SITE "C1" ;
# LOCATE COMP "em_ddr_data[15]" SITE "G3" ;
# LOCATE COMP "em_ddr_dm[0]"    SITE "E3" ;
# LOCATE COMP "em_ddr_dm[1]"    SITE "F3" ;
# LOCATE COMP "em_ddr_dqs[0]"   SITE "F5" ;
# LOCATE COMP "em_ddr_dqs[1]"   SITE "H5" ;
LOCATE COMP "em_ddr_addr[0]" SITE "K5" ;
LOCATE COMP "em_ddr_addr[1]" SITE "N2" ;
LOCATE COMP "em_ddr_addr[2]" SITE "K4" ;
LOCATE COMP "em_ddr_addr[3]" SITE "J1" ;
LOCATE COMP "em_ddr_addr[4]" SITE "V3" ;
LOCATE COMP "em_ddr_addr[5]" SITE "H3" ;
LOCATE COMP "em_ddr_addr[6]" SITE "W1" ;
LOCATE COMP "em_ddr_addr[7]" SITE "H2" ;
LOCATE COMP "em_ddr_addr[8]" SITE "W3" ;
LOCATE COMP "em_ddr_addr[9]" SITE "J7" ;
LOCATE COMP "em_ddr_addr[10]" SITE "M4" ;
LOCATE COMP "em_ddr_addr[11]" SITE "P4" ;
LOCATE COMP "em_ddr_addr[12]" SITE "N1" ;
LOCATE COMP "em_ddr_addr[13]" SITE "A3" ;
LOCATE COMP "em_ddr_addr[14]" SITE "A4" ;
LOCATE COMP "em_ddr_addr[15]" SITE "A2" ;
LOCATE COMP "em_ddr_ba[0]" SITE "R4" ;
LOCATE COMP "em_ddr_ba[1]" SITE "V1" ;
LOCATE COMP "em_ddr_ba[2]" SITE "L2" ;
LOCATE COMP "em_ddr_cke[0]" SITE "M2" ;
LOCATE COMP "em_ddr_clk[0]" SITE "G1" ;
LOCATE COMP "em_ddr_cs_n[0]" SITE "J2" ;
LOCATE COMP "em_ddr_dm[0]" SITE "T4" ;
LOCATE COMP "em_ddr_dm[1]" SITE "P6" ;
LOCATE COMP "em_ddr_dm[2]" SITE "G5" ;
LOCATE COMP "em_ddr_dm[3]" SITE "J4" ;
LOCATE COMP "em_ddr_odt[0]" SITE "P7" ;
LOCATE COMP "em_ddr_reset_n" SITE "T5" ;
LOCATE COMP "em_ddr_data[0]" SITE "Y3" ;
LOCATE COMP "em_ddr_data[1]" SITE "Y1" ;
LOCATE COMP "em_ddr_data[2]" SITE "W2" ;
LOCATE COMP "em_ddr_data[3]" SITE "Y2" ;
LOCATE COMP "em_ddr_data[4]" SITE "U4" ;
LOCATE COMP "em_ddr_data[5]" SITE "AA2" ;
LOCATE COMP "em_ddr_data[6]" SITE "V5" ;
LOCATE COMP "em_ddr_data[7]" SITE "AA1" ;
LOCATE COMP "em_ddr_data[8]" SITE "U2" ;
LOCATE COMP "em_ddr_data[9]" SITE "N5" ;
LOCATE COMP "em_ddr_data[10]" SITE "R3" ;
LOCATE COMP "em_ddr_data[11]" SITE "N3" ;
LOCATE COMP "em_ddr_data[12]" SITE "R1" ;
LOCATE COMP "em_ddr_data[13]" SITE "P1" ;
LOCATE COMP "em_ddr_data[14]" SITE "R2" ;
LOCATE COMP "em_ddr_data[15]" SITE "P3" ;
LOCATE COMP "em_ddr_data[16]" SITE "D1" ;
LOCATE COMP "em_ddr_data[17]" SITE "D4" ;
LOCATE COMP "em_ddr_data[18]" SITE "D2" ;
LOCATE COMP "em_ddr_data[19]" SITE "E4" ;
LOCATE COMP "em_ddr_data[20]" SITE "B2" ;
LOCATE COMP "em_ddr_data[21]" SITE "E5" ;
LOCATE COMP "em_ddr_data[22]" SITE "C2" ;
LOCATE COMP "em_ddr_data[23]" SITE "E3" ;
LOCATE COMP "em_ddr_data[24]" SITE "H4" ;
LOCATE COMP "em_ddr_data[25]" SITE "C1" ;
LOCATE COMP "em_ddr_data[26]" SITE "G2" ;
LOCATE COMP "em_ddr_data[27]" SITE "B1" ;
LOCATE COMP "em_ddr_data[28]" SITE "F3" ;
LOCATE COMP "em_ddr_data[29]" SITE "E2" ;
LOCATE COMP "em_ddr_data[30]" SITE "G3" ;
LOCATE COMP "em_ddr_data[31]" SITE "F1" ;
LOCATE COMP "em_ddr_dqs[0]" SITE "T6" ;
LOCATE COMP "em_ddr_dqs[1]" SITE "P5" ;
LOCATE COMP "em_ddr_dqs[2]" SITE "F5" ;
LOCATE COMP "em_ddr_dqs[3]" SITE "H5" ;
#########################
## READ PULSE CONSTRAINTS
#########################
# LOCATE PGROUP "u_ddr3_sdram_mem_top/U1_ddr3core/U1_ddr3_sdram_phy/read_pulse_delay_0/read_pulse_delay_0" SITE "R13C2D" ;
# LOCATE PGROUP "u_ddr3_sdram_mem_top/U1_ddr3core/U1_ddr3_sdram_phy/read_pulse_delay_1/read_pulse_delay_1" SITE "R22C2D" ;
LOCATE PGROUP "U1_ddr3core/U1_ddr3_sdram_phy/read_pulse_delay_0/read_pulse_delay_0" SITE "R67C2D" ;
LOCATE PGROUP "U1_ddr3core/U1_ddr3_sdram_phy/read_pulse_delay_1/read_pulse_delay_1" SITE "R49C2D" ;
LOCATE PGROUP "U1_ddr3core/U1_ddr3_sdram_phy/read_pulse_delay_2/read_pulse_delay_2" SITE "R13C2D" ;
LOCATE PGROUP "U1_ddr3core/U1_ddr3_sdram_phy/read_pulse_delay_3/read_pulse_delay_3" SITE "R22C2D" ;
###############################################################################################
## DEMO LOGIC
###############################################################################################
#LOCATE COMP "dip_sw[6]" SITE "J2" ;
#LOCATE COMP "dip_sw[7]" SITE "J1" ;
#LOCATE COMP "oled[7]" SITE "V19" ;
###########################################################################
# IO Type Declarations
##########################################################################
IOBUF PORT "clk_in" IO_TYPE=LVDS25 PULLMODE=NONE DIFFRESISTOR=OFF TERMINATEVTT=OFF DRIVE=NA SLEWRATE=FAST PCICLAMP=ON OPENDRAIN=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "reset_n" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=NA SLEWRATE=FAST PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "dip_sw[0]" IO_TYPE=LVCMOS15 TERMINATEVTT=OFF PULLMODE=UP DRIVE=NA SLEWRATE=FAST PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "dip_sw[1]" IO_TYPE=LVCMOS15 TERMINATEVTT=OFF PULLMODE=UP DRIVE=NA SLEWRATE=FAST PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "dip_sw[2]" IO_TYPE=LVCMOS15 TERMINATEVTT=OFF PULLMODE=UP DRIVE=NA SLEWRATE=FAST PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "dip_sw[3]" IO_TYPE=LVCMOS15 TERMINATEVTT=OFF PULLMODE=UP DRIVE=NA SLEWRATE=FAST PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "dip_sw[4]" IO_TYPE=LVCMOS15 TERMINATEVTT=OFF PULLMODE=UP DRIVE=NA SLEWRATE=FAST PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "dip_sw[5]" IO_TYPE=LVCMOS15 TERMINATEVTT=OFF PULLMODE=UP DRIVE=NA SLEWRATE=FAST PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
#IOBUF PORT "dip_sw[6]" IO_TYPE=LVCMOS15 ;
#IOBUF PORT "dip_sw[7]" IO_TYPE=LVCMOS15 ;
IOBUF PORT "oled[0]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "oled[1]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "oled[2]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "oled[3]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "oled[4]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "oled[5]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "oled[6]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
#IOBUF PORT "oled[7]" IO_TYPE=LVCMOS33;
IOBUF PORT "seg[0]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[1]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[2]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[3]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[4]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[5]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[6]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[7]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[8]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[9]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[10]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[11]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[12]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[13]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "seg[14]" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF PULLMODE=UP DRIVE=12 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
BLOCK JTAGPATHS ;
FREQUENCY NET "u_ddr3_sdram_mem_top/sclk2x" 400.000000 MHz PAR_ADJ 80.000000 ;
LOCATE COMP "oled[0]" SITE "E12" ;
IOBUF PORT "em_ddr_odt[0]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_dqs[3]" IO_TYPE=SSTL15D EQ_CAL=0 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" ;
IOBUF PORT "em_ddr_dqs[2]" IO_TYPE=SSTL15D EQ_CAL=0 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" ;
IOBUF PORT "em_ddr_dqs[1]" IO_TYPE=SSTL15D EQ_CAL=0 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" ;
IOBUF PORT "em_ddr_dqs[0]" IO_TYPE=SSTL15D EQ_CAL=0 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" ;
IOBUF PORT "em_ddr_data[5]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[28]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[22]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[11]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[27]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[10]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[21]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[4]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[6]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[29]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[12]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[14]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[18]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[1]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[24]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[7]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[30]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[19]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[2]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[13]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[15]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[25]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[8]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[31]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[26]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[16]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[20]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[3]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[17]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[9]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[0]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_data[23]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=0 ;
IOBUF PORT "em_ddr_clk[0]" IO_TYPE=SSTL15D TERMINATEVTT=OFF PULLMODE=NONE DRIVE=10 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
LOCATE COMP "em_ddr_we_n" SITE "U1" ;
IOBUF PORT "em_ddr_ba[0]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_ba[1]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_ba[2]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[0]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[1]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[2]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[3]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[4]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[5]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[6]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[7]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[8]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[9]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[10]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[11]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[12]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[13]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[14]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_addr[15]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_cs_n[0]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_cke[0]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_dm[3]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_dm[2]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_dm[1]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_dm[0]" IO_TYPE=SSTL15 TERMINATEVTT=OFF PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
LOCATE COMP "dip_sw[5]" SITE "F12" ;
LOCATE COMP "dip_sw[4]" SITE "K3" ;
LOCATE COMP "dip_sw[3]" SITE "L3" ;
LOCATE COMP "dip_sw[2]" SITE "J6" ;
LOCATE COMP "dip_sw[1]" SITE "J3" ;
LOCATE COMP "dip_sw[0]" SITE "L1" ;
LOCATE COMP "seg[14]" SITE "D14" ;
LOCATE COMP "seg[13]" SITE "B14" ;
LOCATE COMP "seg[12]" SITE "A15" ;
LOCATE COMP "seg[11]" SITE "F13" ;
LOCATE COMP "seg[10]" SITE "A14" ;
LOCATE COMP "seg[9]" SITE "F14" ;
LOCATE COMP "seg[8]" SITE "C14" ;
LOCATE COMP "seg[7]" SITE "D13" ;
LOCATE COMP "seg[6]" SITE "C13" ;
LOCATE COMP "seg[5]" SITE "C15" ;
LOCATE COMP "seg[4]" SITE "A16" ;
LOCATE COMP "seg[3]" SITE "E16" ;
LOCATE COMP "seg[2]" SITE "D15" ;
LOCATE COMP "seg[1]" SITE "G14" ;
LOCATE COMP "seg[0]" SITE "B16" ;
LOCATE COMP "oled[6]" SITE "B12" ;
LOCATE COMP "oled[5]" SITE "A13" ;
LOCATE COMP "oled[4]" SITE "E13" ;
LOCATE COMP "oled[3]" SITE "D12" ;
LOCATE COMP "oled[2]" SITE "B11" ;
LOCATE COMP "oled[1]" SITE "C12" ;
LOCATE COMP "reset_n" SITE "G22" ;
LOCATE COMP "em_ddr_cas_n" SITE "L4" ;
LOCATE COMP "em_ddr_ras_n" SITE "M1" ;
lattice
评分
欢迎为Ta评分
分享
请登录后发表评论

    回复3
    只看作者
    最新最热
    • yang9527的头像-ChipDebugyang9527徽章-资深玩家-ChipDebug等级-LV1-ChipDebug0

      碰到同样的问题，正好用楼上的办法解决了，，谢谢！

      6年前
    • Zack的头像-ChipDebugZack徽章-资深玩家-ChipDebug等级-LV1-ChipDebug1

      注意lpf文件中这几个管脚的group约束,

      DEFINE PORT GROUP "EM_DDR_BA_GRP" "em_ddr_ba[*]" ;
IOBUF GROUP "EM_DDR_BA_GRP" IO_TYPE=SSTL15 BANK=0 DRIVE=8 ;
IOBUF PORT "em_ddr_ras_n" IO_TYPE=SSTL15 DRIVE=8 TERMINATEVTT=OFF PULLMODE=NONE SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_cas_n" IO_TYPE=SSTL15 DRIVE=8 TERMINATEVTT=OFF PULLMODE=NONE SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;
IOBUF PORT "em_ddr_we_n" IO_TYPE=SSTL15 DRIVE=8 TERMINATEVTT=OFF PULLMODE=NONE SLEWRATE=SLOW PCICLAMP=ON OPENDRAIN=OFF DIFFRESISTOR=OFF DIFFDRIVE="NA" MULTDRIVE="NA" EQ_CAL=NA ;

      注意到IOBUF GROUP "EM_DDR_ADDR_GRP" IO_TYPE=SSTL15 BANK=0 DRIVE=8 ;这一句了吗？ 将它改为IOBUF GROUP "EM_DDR_ADDR_GRP" IO_TYPE=SSTL15 BANK=6 DRIVE=8 ;就可以了。

      6年前
搜索
开启精彩搜索
FPGA SOC ARM RISCV IC 开发调试技术交流分享
FPGA SOC ARM RISCV IC 开发调试技术交流分享
FPGA SOC ARM RISCV IC 开发调试技术交流分享
热门帖子

在手机上浏览此页面