LATTICE XO3 EBR 块RAM使用量优化请教？

5年前发布

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大家好，我用LATTICE XO3-4300做MIPI DSI to RGB888以及简单的2D梯形校正的设计,发现仅MIPI DSI RX就使用了一半的EBR块RAM，而我后面的算法也差不多要用一半的RAM，那么这个设计看起来似乎没有办法完成了。MIPI DSI RX我使用的是LATTICE 的RD1185这个参考设计，大伙有没有什么建议，要以优化EBR的大小，我的逻辑量使用得很少。

Design Summary
   Number of registers:    536 out of  4512 (12%)
      PFU registers:          535 out of  4320 (12%)
      PIO registers:            1 out of   192 (1%)
   Number of SLICEs:       292 out of  2160 (14%)
      SLICEs as Logic/ROM:    292 out of  2160 (14%)
      SLICEs as RAM:            0 out of  1620 (0%)
      SLICEs as Carry:         16 out of  2160 (1%)
   Number of LUT4s:        410 out of  4320 (9%)
      Number used as logic LUTs:        378
      Number used as distributed RAM:     0
      Number used as ripple logic:       32
      Number used as shift registers:     0
   Number of PIO sites used: 45 + 4(JTAG) out of 64 (77%)
      Number of PIO sites used for single ended IOs: 43
      Number of PIO sites used for differential IOs: 6 (represented by 3 PIO
     comps in NCD)
   Number of IDDR/ODDR/TDDR cells used: 2 out of 192 (1%)
      Number of IDDR cells:   2
      Number of ODDR cells:   0
      Number of TDDR cells:   0
   Number of PIO using at least one IDDR/ODDR/TDDR: 2 (2 differential)
      Number of PIO using IDDR only:        2 (2 differential)
      Number of PIO using ODDR only:        0 (0 differential)
      Number of PIO using TDDR only:        0 (0 differential)
      Number of PIO using IDDR/ODDR:        0 (0 differential)
      Number of PIO using IDDR/TDDR:        0 (0 differential)
      Number of PIO using ODDR/TDDR:        0 (0 differential)
      Number of PIO using IDDR/ODDR/TDDR:   0 (0 differential)
   Number of block RAMs:  5 out of 10 (50%)
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)

   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  1 out of 2 (50%)
   Number of DQSDLLs:  0 out of 2 (0%)

lattice

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`define word_alignment //Turns on byte alignment; aligns byte data to single byte clock cycle based on HS-Sync Sequence `define lane_alignment //Turns on lane alignment; aligns lanes to same byte clock cycle based on HS-Sync Sequence //`define crossclkfifo //Adds cross clock fifo and free running clock input to D-PHY RX Interface IP

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