【分享】ALTERA FPGA 使用axf文件生成用于裸机SD卡启动的相关命令

arm-altera-eabi-gcc -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -Wall -Wl,--defsym -Wl,arm_program_mem=0x40 -Wl,--defsym -Wl,arm_available_mem_size=0x3fffffb8 -Wl,--defsym -Wl,__cs3_stack=0x3ffffff8 -Wl,--section-start -Wl,.vectors=0x0 -T"D:/intelFPGA/17.1/University_Program/Monitor_Program/build/altera-socfpga-hosted-with-vectors.ld" -o "F:/FPGA/Firmware/01_Project/ARM/exp6/interrupt_example.axf" "F:/FPGA/Firmware/01_Project/ARM/exp6/interrupt_example.c" "F:/FPGA/Firmware/01_Project/ARM/exp6/exceptions.c" "F:/FPGA/Firmware/01_Project/ARM/exp6/HPS_timer_ISR.c" "F:/FPGA/Firmware/01_Project/ARM/exp6/interval_timer_ISR.c" "F:/FPGA/Firmware/01_Project/ARM/exp6/JTAG_UART.c" "F:/FPGA/Firmware/01_Project/ARM/exp6/pushbutton_ISR.c" 
ELF generated at F:/FPGA/Firmware/01_Project/ARM/exp6/interrupt_example.axf.
cd F:/FPGA/Firmware/01_Project/ARM/exp6 ; arm-altera-eabi-objcopy -O srec interrupt_example.axf interrupt_example.srec 
SREC generated at F:/FPGA/Firmware/01_Project/ARM/exp6/interrupt_example.srec.
Generating binaries for use with U-Boot Baremetal SD Card ...
Creating the user program binary (program.bin) ...
arm-altera-eabi-objcopy --output-target=binary F:/FPGA/Firmware/01_Project/ARM/exp6/interrupt_example.axf F:/FPGA/Firmware/01_Project/ARM/exp6/program.bin 
Creating the FPGA programming file (fpga.rbf) ...
quartus_cpf --option="bitstream_compression=on" -c --configuration_mode=FPP ../Computer_Systems/DE1-SoC/DE1-SoC_Computer/verilog/DE1_SoC_Computer.sof F:/FPGA/Firmware/01_Project/ARM/exp6/fpga.rbf 
Info: *******************************************************************
Info: Running Quartus Prime Convert_programming_file
    Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Jan 09 17:54:26 2019
Info: Command: quartus_cpf --option=bitstream_compression=on -c --configuration_mode=FPP ../Computer_Systems/DE1-SoC/DE1-SoC_Computer/verilog/DE1_SoC_Computer.sof F:/FPGA/Firmware/01_Project/ARM/exp6/fpga.rbf
Info: Quartus Prime Convert_programming_file was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 345 megabytes
    Info: Processing ended: Wed Jan 09 17:54:28 2019
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02
Creating the U-Boot environment setup script (setup_environment.bin) ...
arm-altera-eabi-readelf --symbols F:/FPGA/Firmware/01_Project/ARM/exp6/interrupt_example.axf 
Entrypoint (_start) address: 0x00000128
mkimage -T script -C none -n 'setup_environment' -d script.temp setup_environment.bin 
Image Name:   setup_environment
Created:      Wed Jan 09 17:54:30 2019
Image Type:   PowerPC Linux Script (uncompressed)
Data Size:    53 Bytes = 0.05 kB = 0.00 MB
Load Address: 00000000
Entry Point:  00000000
Contents:
   Image 0: 45 Bytes = 0.04 kB = 0.00 MB

Finished generating binaries for U-Boot Baremetal SD Card.