请教给位大佬，怎么实现两个数据信号的优先级控制-FPGA常见问题社区-FPGA CPLD-ChipDebug
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    • 的头像-ChipDebug三尽等级-LV1-ChipDebug1

      优先级控制可以直接使用if else，
      if（uart_en_1）begin
      end
      else if（uart_en_2）begin
      end

      6年前
    • 的头像-ChipDebug老陳等级-LV1-ChipDebug0

      自己寫仲裁很簡單
      兩個同時到 就用輪流方式 A B A B
      沒人搶 先到 先做

      6年前
    • chipdebug的头像-ChipDebugchipdebug等级-LV4-ChipDebug超级版主0

      看看RTL综合工具的描述就知道了。

      7年前

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