vivado功能仿真ERROR: [Common 17-39] ‘launch_simulation’ failed due to earlier errors.

Vivado Simulator 2017.4
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Running: D:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto 513e6709b0884fc19e18577b87720c96 –incr –debug typical –relax –mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip –snapshot test_dtrig_behav xil_defaultlib.test_dtrig xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-2538] module instantiation should have an instance name [C:/Users/dell/Desktop/dtrig/dtrig.srcs/sim_1/new/test_dtrig.v:31]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

我打开elaborate.log是上述信息，请指导错误的原因，初学者，多请教大家，盼望不吝赐教。