Lattice LIF-MD6000使用 mipi d-phy to CMOS接上refclk時編譯不過

看清楚这句话，the clock refclk_i_c on comp dphy2cmos/dphy2cmos_inst/genblk1.snow_pll_wrapper_inst/PLLInst_0 port CLKI is driven by general routing through comp refclk_i.

要么换管脚，要么加个约束屏蔽掉这个，但是建议最终做产品时仍然换个符合规则的管脚。约束的话我回头找找发上来。