求问PLL时钟输出引脚在ucf文件中该如何编写

我想用块DAC做DDS输出，用PLL分频输出20MHz给DAC芯片，代码如下：
module top(
input clk,
input rst_n,
input on,
output reg dacfs,
output sclk,
output reg din
);

//state
localparam IDLE = 0;
localparam FRAMESYNC = 1;
localparam READ = 2;
localparam STOP = 3;

reg [3-1:0] state;
reg [3-1:0] next_state;

//dds input and output
reg sclk_r;
reg [32-1:0] Fword;
reg [32-1:0] Fword_r;
reg [12-1:0] Pword;
reg [12-1:0] Pword_r;
wire [12-1:0] data;
reg [32-1:0] Fcnt;
reg [12-1:0] rom_addr;

//DAC input
wire [4-1:0] din_control;
reg [16-1:0] din_data;
reg [5-1:0] data_cnt;
reg din_r; //din_r = din_data<cnt>
reg fs_r;

//clk pll to sclk
IBUFG IBUFG_INST
(
.O(clk_bufg),
.I(clk)
);

pll pll_dac
(
.clk_in(clk_bufg),
.clk_out(sclk),
.reset(~rst_n)
);

//data generation

always@(negedge sclk)
begin
Fword_r <= Fword;
Pword_r <= Pword;
end

always@(negedge sclk)
rom_addr <= Fcnt[32-1:20] + Pword_r;

rom rom(
.addra(rom_addr),
.clka(sclk),
.douta(data)
);

always@(posedge sclk or negedge rst_n)
begin
if(~rst_n)
state <= IDLE;
else
state <= next_state;
end

always@(negedge sclk)
begin
if(~rst_n)
begin
next_state <= IDLE;
fs_r <= 0;
end
else if(~on)
case(state)
IDLE:
begin
fs_r <= 1;
next_state <= FRAMESYNC;
end
FRAMESYNC:
begin
fs_r <= 0;
next_state <= READ;
end
READ:
if(data_cnt <= 4’d16)
begin
data_cnt <= data_cnt + 4’d1;
din_r <= din_data[data_cnt];
end
else
next_state <= STOP;
STOP:
if(Fcnt < 32’d4095)
begin
next_state <= IDLE;
Fcnt <= Fcnt + Fword_r;
data_cnt <= 4’d0;
end
else
begin
next_state <= IDLE;
Fcnt <= 32’d0;
data_cnt <= 4’d0;
end
default:
begin
next_state <= IDLE;
Fcnt <= 32’d0;
data_cnt <= 4’d0;
end
endcase
end
//din signal
assign din_control = 4’b0110;
always@(*)
begin
din_data[16-1:12] <= din_control[3:0];
din_data[11:0] <= data[11:0];
dacfs <= fs_r;
end

always@(negedge sclk)
begin
din <= din_r;
end

endmodule
然后我在编写ucf文件
NET clk LOC = T8 | TNM_NET = sys_clk_pin | IOSTANDARD = “LVCMOS33”;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;

NET rst_n LOC = L3 | IOSTANDARD = “LVCMOS33”; ## reset pushbutton
NET on LOC = C3 | IOSTANDARD = “LVCMOS33”; ## start to read
NET dacfs LOC = D3 | IOSTANDARD = “LVCMOS33”; ## FYAME
NET sclk LOC = K16 | IOSTANDARD = “LVCMOS33”; ## sclk-PIN
NET din LOC = P5 | IOSTANDARD = “LVCMOS33”; ## output

PIN “pll_dac/sclk_buf.O” CLOCK_DEDICATED_ROUTE = FALSE;

调试后报错为：
ERROR:ConstraintSystem:59 – Constraint <pin “pll_dac=”” sclk_buf.o”=”” clock_dedicated_route=”FALSE;”> [dac_pin.ucf(10)]: PIN
“pll_dac/sclk_buf.O” not found. Please verify that:

1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

发现问题是在“PIN “pll_dac/sclk_buf.O” CLOCK_DEDICATED_ROUTE = FALSE;”这一段上，而我参考的pll教程中的ucf文件是下面这一段代码：

##
NET clk LOC = T8 | TNM_NET = sys_clk_pin | IOSTANDARD = “LVCMOS33”;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;

##

##
NET rst_n LOC = L3 | IOSTANDARD = “LVCMOS33”; ##

##

########SMA Clock out define#####################
NET clkout1 LOC = K16 | IOSTANDARD = “LVCMOS33”; ## J2-PIN3
NET clkout2 LOC = J16 | IOSTANDARD = “LVCMOS33”; ## J2-PIN4
NET clkout3 LOC = L16 | IOSTANDARD = “LVCMOS33”; ## J2-PIN5
NET clkout4 LOC = K15 | IOSTANDARD = “LVCMOS33”; ## J2-PIN6

PIN “pll_inst/clkout4_buf.O” CLOCK_DEDICATED_ROUTE = FALSE;
PIN “pll_inst/clkout3_buf.O” CLOCK_DEDICATED_ROUTE = FALSE;
PIN “pll_inst/clkout2_buf.O” CLOCK_DEDICATED_ROUTE = FALSE;
PIN “pll_inst/clkout1_buf.O” CLOCK_DEDICATED_ROUTE = FALSE;

我是仿照着教程的代码编写，教程能成功运行，但我自己的代码却不能，不知道我自己写的ucf问题出在哪里，所以希望能得到各位大佬的指点