cyclone10 GX的芯片对芯片的demo, 主要代码如下，其实主要是IP的配置，别的没啥可说的。
`timescale 1 ns / 1 ps
module native_loopback(
input clk_ref,
input clk_125m,
input reset,
input run,
//output wire tx_clkout/*synthesis keep*/,
output wire [1:0]rx_clkout,
output [7:0] rx_parallel_data/*synthesis preserve*/,
output [7:0] rx_parallel_data2/*synthesis preserve*/,
input [1:0] rx_serial_data,
output [1:0] tx_serial_data,
output [1:0] rx_patterndetect,
output [1:0] rx_disperr,
output [1:0] rx_errdetect,
output [1:0] rx_runningdisp,
output [1:0] rx_syncstatus,
output [1:0] rx_datak_r,
output error_flag,
output [1:0] rx_is_lockedtoref,
output error
);
wire pll_powerdown_r;
wire tx_clk_1250M;
wire pll_cal_busy_r;
wire pll_locked_r;
wire [1:0]rx_analogreset_r;
wire [1:0]rx_cal_busy_r;
wire [1:0]rx_digitalreset_r;
wire [1:0]rx_is_lockedtodata_r;
wire [1:0]rx_ready_r;
wire [1:0]tx_analogreset_r;
wire [1:0]tx_cal_busy_r;
wire [1:0]tx_digitalreset_r;
wire [1:0]tx_ready_r;
//wire rx_clkout;
wire [1:0]tx_clkout;
reg [1:0]tx_datak;
wire rx_syncstatus_r;
wire [116:0] unused_rx_data_r;
// wire [1:0] rx_datak_r;
wire [39:0] rx_parallel_data_r,rx_parallel_data_r2;
reg tx_datak_r;
reg [7:0] tx_parallel_data_r,tx_parallel_data_r2;
wire [7:0] tx_parallel_data_r1;
wire [7:0] rx_data/*synthesis preserve*/,rx_data2/*synthesis preserve*/;
reg [7:0] data_error;
wire error_en;
//------------------------------------------------------------------------
// 闂傚倸鍊风粈渚€骞栭锕€鐤い鎰堕檮閸嬪鈹戦崒婊庣劸缂佺姳鍗抽弻鐔兼倷椤掑倻鐛梺缁樻⒒閸樠囨倶閹惰姤鐓ｉ煫鍥风到娴滄粌霉 //------------------------------------------------------------------------
ATX_PLL_CLK ATX_PLL_CLK( .pll_refclk0 ( clk_125m ),
.pll_powerdown ( pll_powerdown_r ),
.tx_serial_clk ( tx_clk_1250M ),
.pll_cal_busy ( pll_cal_busy_r ),
.pll_locked ( pll_locked_r )
);
//------------------------------------------------------------------------
// 濠电姷鏁告慨浼村垂閻撳簶鏋栨繛鎴炴皑閻挾鈧娲栧ú銊х矆婵犲洦鐓曟繛鎴濆船鐢綁鏌ｉ弮鍌氬付闁诲繑濞婇弻褑绠涢敐鍛盎婵/------------------------------------------------------------------------
reset_native reset_native( .clock ( clk_125m ),
.reset ( !reset ),
.pll_locked ( pll_locked_r ),
.pll_powerdown ( pll_powerdown_r ),
.pll_select ( 1'b0 ),
.rx_analogreset ( rx_analogreset_r),
.rx_cal_busy ( {rx_cal_busy_r[1],1'b0} ),
.rx_digitalreset( rx_digitalreset_r),
.rx_is_lockedtodata( {rx_is_lockedtodata_r[1],1'b1} ),
.rx_ready ( rx_ready_r ),
.tx_analogreset ( tx_analogreset_r ),
.tx_cal_busy ( {tx_cal_busy_r[1],1'b0} ),
.tx_digitalreset( tx_digitalreset_r ),
.tx_ready ( tx_ready_r )
);
//------------------------------------------------------------------------
// PHY婵犵數濮烽。钘壩ｉ崨鏉戝瀭妞ゅ繐鐗嗛悞鍨亜閹烘垵鏆為柣婵愪邯閺/------------------------------------------------------------------------
native_phy_1g native_phy_1g( .rx_analogreset ( rx_analogreset_r[0] ),
.rx_cal_busy ( rx_cal_busy_r[0] ),
.rx_cdr_refclk0 ( clk_125m ),
.rx_clkout ( rx_clkout[0] ),
.rx_coreclkin ( rx_clkout[0] ),
.rx_datak ( rx_datak_r[0] ),
.rx_digitalreset ( rx_digitalreset_r[0] ),
.rx_disperr (rx_disperr[0]),
.rx_errdetect (rx_errdetect[0]),
.rx_is_lockedtodata ( rx_is_lockedtodata_r[0] ),
.rx_is_lockedtoref ( rx_is_lockedtoref[0] ),
.rx_parallel_data ( rx_parallel_data_r ),
.rx_patterndetect (rx_patterndetect[0]),
.rx_rmfifostatus (),
.rx_runningdisp (rx_runningdisp[0]),
.rx_serial_data ( rx_serial_data[0] ),
.rx_seriallpbken ( 1'b0 ),
.rx_syncstatus (rx_syncstatus[0] ),
.tx_analogreset ( tx_analogreset_r[0] ),
.tx_cal_busy ( tx_cal_busy_r[0] ),
.tx_clkout ( tx_clkout[0] ),
.tx_coreclkin ( tx_clkout[0] ),
.tx_datak ( tx_datak[0] ),
.tx_digitalreset ( tx_digitalreset_r[0] ),
.tx_parallel_data ( tx_parallel_data_r ),
.tx_serial_clk0 ( tx_clk_1250M ),
.tx_serial_data ( tx_serial_data[0] ),
.unused_rx_parallel_data( ),
.unused_tx_parallel_data( 119'b0 )
);
native_phy_1g native_phy_1g_2( .rx_analogreset ( rx_analogreset_r[1] ),
.rx_cal_busy ( rx_cal_busy_r[1] ),
.rx_cdr_refclk0 ( clk_125m ),
.rx_clkout ( rx_clkout[1] ),
.rx_coreclkin ( rx_clkout[1] ),
.rx_datak ( rx_datak_r[1] ),
.rx_digitalreset ( rx_digitalreset_r[1] ),
.rx_disperr (rx_disperr[1]),
.rx_errdetect (rx_errdetect[1]),
.rx_is_lockedtodata ( rx_is_lockedtodata_r[1] ),
.rx_is_lockedtoref ( rx_is_lockedtoref[1] ),
.rx_parallel_data ( rx_parallel_data_r2 ),
.rx_patterndetect (rx_patterndetect[1]),
.rx_rmfifostatus (),
.rx_runningdisp (rx_runningdisp[1]),
.rx_serial_data ( rx_serial_data [1] ),
.rx_seriallpbken ( 1'b0 ),
.rx_syncstatus (rx_syncstatus[1]),
.tx_analogreset ( tx_analogreset_r[1] ),
.tx_cal_busy ( tx_cal_busy_r[1] ),
.tx_clkout ( tx_clkout[1] ),
.tx_coreclkin ( tx_clkout[1] ),
.tx_datak ( tx_datak[1] ),
.tx_digitalreset ( tx_digitalreset_r[1] ),
.tx_parallel_data ( tx_parallel_data_r2 ),
.tx_serial_clk0 ( tx_clk_1250M ),
.tx_serial_data ( tx_serial_data[1]),
.unused_rx_parallel_data( ),
.unused_tx_parallel_data( 119'b0 )
);
always@(posedge tx_clkout[0] or negedge reset)
begin
if(!reset )
tx_parallel_data_r <= 8'b0;
else if(run)
tx_parallel_data_r <= tx_parallel_data_r +1;
else
tx_parallel_data_r <= 8'hbc ; //tx_parallel_data_r +1;
end
always@(posedge tx_clkout[1] or negedge reset)
begin
if(!reset )
tx_parallel_data_r2 <= 8'b0;
else if(run)
tx_parallel_data_r2 <= tx_parallel_data_r2 +1;
else
tx_parallel_data_r2 <= 8'hbc ; //tx_parallel_data_r2 +1;
end
assign tx_parallel_data_r1 = tx_parallel_data_r;
assign rx_data = rx_parallel_data_r[7:0];
assign rx_parallel_data = rx_parallel_data_r[7:0];
assign rx_data2 = rx_parallel_data_r2[7:0];
assign rx_parallel_data2 = rx_parallel_data_r2[7:0];
wire test;
always@(posedge tx_clkout[0] or negedge reset)
begin
if(!reset )
tx_datak[0] <= 1'b0;
else if(run)
tx_datak[0] <= 1'b0;
else
tx_datak[0] <= 1'b1;
end
always@(posedge tx_clkout[1] or negedge reset)
begin
if(!reset )
tx_datak[1] <= 1'b0;
else if(run)
tx_datak[1] <= 1'b0;
else
tx_datak[1] <= 1'b1;
end
// always@(posedge tx_clkout[1] or negedge reset)
// begin
// if(!reset )
// error_en <= 1'b0;
// else if(rx_data2 == 8'hff)
// error_en <= 1'b1;
// else if(!run)
// error_en <= 1'b0;
// end
always@(posedge tx_clkout[1] or negedge reset)
begin
if(!reset )
data_error <= 8'b0;
else if(error_en)
data_error <= data_error + 1'b1;
else
data_error <= 8'b0;
end
assign error_flag = data_error != rx_data2;
debug_io u_debug_io (
.source (error_en), // output, width = 1, sources.source
.source_clk (tx_clkout[1]), // input, width = 1, source_clk.clk
.probe (error_flag) // input, width = 1, probes.probe
);
endmodule
工程如下，自取不谢！
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