Xilinx vivado中7系列FPGA(SPARTAN7 KINTEX7 ARTIX7 VIRTEX7) DDR3控制器MIG IP应用最详细的调试笔记

popomao

2年前更新

140

MIG配置界面详解

DDR3时钟、参考时钟为固定200M，系统复位极性，阻抗选择，VCCAUX，DCI选项

## DIMM的RANK解释R1x8，1333与DDR3时钟频率的

关系

## DDR3的硬件调试，及信号调试

## ILA PROBE用法

添加超过64个probe的方法

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VIO用法

assign system_reset = ( cpu_reset );

       vio_0 VIO_inst(
          .clk       (  input_clk_div   ),
          .probe_in0 (  led[3:0]  ),
          .probe_out0(  reset_in  ) //assumes a positive going reset, initialized to 0!!
       );

       always @(posedge CFGMCLK)begin :ONESHOT
          if (reset_in & counter > 0)	begin
       	     cpu_reset <= 1;
       	     counter   <= counter - 1;
       	  end
       	  else if (reset_in & counter == 0) begin
       	     cpu_reset <= 0;
       	     counter   <= 0;
       	  end
       	  else begin
       	     cpu_reset <= 0;
       	     counter   <= 7;
       	  end
       end

STARTUPE2用法

STARTUPE2 #(
      .PROG_USR("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.
      .SIM_CCLK_FREQ(0.0)  // Set the Configuration Clock Frequency(ns) for simulation.
   )
   STARTUPE2_inst (
      .CFGCLK(CFGCLK),       // 1-bit output: Configuration main clock output
      .CFGMCLK(CFGMCLK),     // 1-bit output: Configuration internal oscillator clock output
      .EOS(EOS),             // 1-bit output: Active high output signal indicating the End Of Startup.
      .PREQ(PREQ),           // 1-bit output: PROGRAM request to fabric output
      .CLK(CLK),             // 1-bit input: User start-up clock input
      .GSR(GSR),             // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
      .GTS(GTS),             // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
      .KEYCLEARB(KEYCLEARB), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
      .PACK(PACK),           // 1-bit input: PROGRAM acknowledge input
      .USRCCLKO(USRCCLKO),   // 1-bit input: User CCLK input
      .USRCCLKTS(USRCCLKTS), // 1-bit input: User CCLK 3-state enable input
      .USRDONEO(USRDONEO),   // 1-bit input: User DONE pin output control
      .USRDONETS(USRDONETS)  // 1-bit input: User DONE 3-state enable output
   );

### 最简测试代码，两个模块，一个产生一次突发读写，另一个用来进行反复突然读写

### 官方DDR3examp_top说明

### PBRS校验是7系列FPGA DDR3 MIG控制器中才加进来的功能

每一bit都错，真是没救了。

## bit转MCS烧录flash

write_cfgmem -format mcs -interface bpix16 -size 64 -loadbit "up 0x0 [get_property DIRECTORY [current_project]]/[current_project].runs/impl_1/[get_property TOP [get_filesets sources_1]].bit" -force -file [get_property DIRECTORY [current_project]].mcs

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