易灵思FPGA-原语使用指南（不间断更新）

yzllee

2年前更新

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易灵思FPGA-原语使用指南

原语手册
原语使用

原语手册

打开Efinity ，在菜单栏的help中Documentation里面可以找到对应的原语PDF手册

在 Efiniry 安装路径下，可以找到所有的底层原语仿真模型，modelsim 仿真的时候需要；

原语使用

DSP Block—EFX_DSP48

一般做法建议直接乘号 * 最简单；如果有符号的直接 reg signed ；综合器跑一下就知道用了多少个DSP资源了；

如果用法特别精细的话，那就是直接用DSP的原语了，笔者在这只是举个例子，用户可以根据实际情况用 EFX_DSP48 ，EFX_DSP24 ，EFX_DSP12 ；
当然觉得用的麻烦的话，当然还有简单的版本；

// DSP48 Instantiation Template
EFX_DSP48 #(
 .MODE ("NORMAL"), // Normal mode 
 .A_REG (0), // enable A-register 
 .B_REG (0), // enable B-register
 .C_REG (0), // enable C-register
 .P_REG (0), // enable P-register
 .OP_REG (0), // enable OP-register
 .W_REG (0), // enable W-register
 .O_REG (0), // enable O-register
 .RST_SYNC (0), // set sync/async reset 
 .SIGNED (1), // set signed/unsigned multiply
 .P_EXT ("ALIGN_RIGHT"), // left/right alignment for P 
 .C_EXT ("ALIGN_RIGHT"), // left/right alighment for C
 .M_SEL ("P"), // select M-input to the adder 
 .N_SEL ("C"), // select N-input to the adder 
 .W_SEL ("X"), // select input to the shifter 
 .CASCOUT_SEL ("W"), // select cascout 
 .CLK_POLARITY (1), // clk polarity 
 .CE_POLARITY (1), // ce polarity 
 .RST_POLARITY (1), // rst polarity 
 .SHIFT_ENA_POLARITY (1), // shift_ena polarity 
 .ROUNDING ("RNE"), // rounding method
 .A_REG_USE_CE (1), // A-register use clock enable
 .B_REG_USE_CE (1), // B-register use clock enable
 .C_REG_USE_CE (1), // C-register use clock enable
 .OP_REG_USE_CE (1), // OP-register use clock enable
 .P_REG_USE_CE (1), // P-register use clock enable
 .W_REG_USE_CE (1), // W-register use clock enable
 .O_REG_USE_CE (1), // Oregister use clock enable
 .A_REG_USE_RST (1), // A-register use reset
 .B_REG_USE_RST (1), // B-register use reset
 .C_REG_USE_RST (1), // C-register use reset
 .OP_REG_USE_RST (1), // OP-register use reset
 .P_REG_USE_RST (1), // P-register use reset
 .W_REG_USE_RST (1), // W-register use reset
 .O_REG_USE_RST (1) // O-register use reset
 )
 dsp48_inst (
 .A (A), // 19-bit A input 
 .B (B), // 18-bit B input 
 .C (C), // 17-bit C input 
 .CASCIN(0), // 48-bit cascin from another DSP block 
 .OP (2'b00), // 2-bit operation mode
 .SHIFT_ENA(1'b1), // 1-bit shift_ena input
 .CLK (clk), // 1-bit clock
 .CE (ce), // 1-bit clock enable
 .RST (rst), // 1-bit reset
 .O (O), // 48-bit output
 .CASCOUT(), // 48-bit cascout, hard-wired to another DSP block
 .OVFL() // 1-bit overflow flag
);

像DSP48 ： A B 是输入，C是加数，O的结果是 A*B+C ；
在5个周期后出结果，复位是瞬时复位；
建议传导的参数都使用默认的，要么就自己研究下手册和原语代码，否则可能综合不过去；

EFX_ADD

EFX_COMB4

EFX_ADD

EFX_DPRAM10

原语库里面能看到有 5K 10K 的双口Ram ，真双口Ram ，根据需求自己调用；
如图是 10kbit 真双口的配置接口选项；

// EFX_DPRAM10 Instantiation Template
EFX_DPRAM10 # (
 .CLKA_POLARITY (1'b1), // clka polarity
 .CLKEA_POLARITY (1'b1), // clkea polarity
 .WEA_POLARITY (1'b1), // wea polarity
 .ADDRENA_POLARITY (1'b1), // addrena polarity
 .RSTA_POLARITY (1'b1), // rsta polarity
 .CLKB_POLARITY (1'b1), // clkb polarity
 .CLKEB_POLARITY (1'b1), // clkeb polarity
 .WEB_POLARITY (1'b1), // web polarity
 .ADDRENB_POLARITY (1'b1), // addrenb polarity
 .RSTB_POLARITY (1'b1), // rstb polarity
 .READ_WIDTH_A (8), // A-port read width
 .WRITE_WIDTH_A (8), // A-port write width
 .READ_WIDTH_B (8), // B-port read width
 .WRITE_WIDTH_B (8), // B-port write width
 .OUTPUT_REG_A (1'b0), // A-port output register enable
 .OUTPUT_REG_B (1'b0), // B-port output register enable
 .WRITE_MODE_A ("READ_FIRST"), // A-port write mode
 .WRITE_MODE_B ("READ_FIRST"), // B-port write mode
 .RESET_RAM_A ("ASYNC"), // A-port reset mode on ram 
 .RESET_RAM_B ("ASYNC"), // B-port reset mode on ram 
 .RESET_OUTREG_A ("ASYNC"), // A-port reset mode on output register
 .RESET_OUTREG_B ("ASYNC"), // B-port reset mode on output register
 
 // 256-bit INIT string
 .INIT_0 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_1 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_2 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_3 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_4 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_5 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_6 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_7 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_8 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_9 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_A (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_B (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_C (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_D (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_E (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_F (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
 .INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000)
 )
 dpram10_inst (
 .CLKA (CLKA), // A-port clk 
 .WEA (WEA), // A-port write enable 
 .CLKEA (CLKEA), // A-port clk enable	持续给1就行
 .RSTA (RSTA), // A-port reset 
 .ADDRENA (ADDRENA), // A-port address enable	持续给1就行
 .WDATAA (WDATAA), // A-port write data input
 .ADDRA (ADDRA), // A-port address input
 .RDATAA (RDATAA), // A-port read address output
 .CLKB (CLKB), // B-port clk 
 .WEB (WEB), // B-port write enable 
 .CLKEB (CLKEB), // B-port clk enable	持续给1就行 	
 .RSTB (RSTB), // B-port reset 
 .ADDRENB (ADDRENB), // B-port address enable	持续给1就行
 .WDATAB (WDATAB), // B-port write data input
 .ADDRB (ADDRB), // B-port address input
 .RDATAB (RDATAB) // B-port read address output
 );

一大串INIT 是对ram 内存储数据的初始化；READ/WRITE_WIDTH_A/B 填 8 ，是default 1024 x 8 ，可以根据手册自已定义，配置不同的读写位宽；

剩下的一些参数都没啥特别需要说明的；