我自己写了一个FPGA 的 fifo总有问题，不知道什么原因？问问大家能否解决

贴一段网上的异步FIFO代码给你，

module async_fifO(
       wclk,
       wr,
       wdat,
       wr_full,
       rclk,
       rd,
       rdat,
       rd_empty,
       resetb
);

parameter DW   = 16;
          AW   = 8;
          DP   = 1<<AW;

input           wclk;
input           wr;
input  [DW-1:0] wdat;
output          wr_full;
input           rclk;
input           rd;
output [DW-1:0] rdat;
output          rd_empty;
input           resetb;
parameter ck2q = 1;

//
//////////////////////////////////////////////////////
// dpram
wire wire_wr = wr && !wr_full;
wire wire_rd = rd && !rd_empty;

dpram    u_dpram(
        .wclk   ( wr_clk  ),
        .wr     ( wire_wr ),
        .waddr  ( waddr   ),
        .wdat   ( wdat    ),
        .rclk   ( rclk    ),
        .rd     ( wire_rd ),
        .raddr  ( raddr   ),
        .rdat   ( rdat    )
);


//
//////////////////////////////////////////////////////
// write address

//============waddr+1=========== 
reg  [AW:0  ] waddr;
wire [AW-1:0] waddr_p1 = waddr + 1'b1;
always@(posedge clkin or negedge resetb)begin
    if(!resetb)
        waddr <= #ck2q 0;
    else if(ie) begin
        waddr <= #ck2q waddrp1;
    end
end
//========bcd to gray reg========
wire [AW:0] waddr_g;
assign      waddr_g[AW]    = waddr_g[AW];
assign      waddr_g[AW-1:0]= waddr_g ^ waddr_g>>1;
reg  [AW:0] waddr_g_w0;
always@(posedge clkin or negedge resetb)begin
    if(!resetb)
        waddr_g_w0 <= #ck2q 0;
    else if(ie) begin
        waddr_g_w0 <= #ck2q waddr_g;
    end
end
//========waddr to rclk domain========
reg  [AW:0] waddr_g_r0,waddr_g_r1;
always@(posedge clkout or negedge resetb)begin
    if(!resetb)begin
        waddr_g_r0 <= #ck2q 0;
        waddr_g_r1 <= #ck2q 0;
    end
    else begin
        waddr_g_r0 <= waddr_g_w0;
        waddr_g_r1 <= waddr_g_r0;
    end
end
//=========gray to bcd========
reg [AW:0] waddr_r1;
integer j;
always@(waddr_g_r1)begin
        waddr_r1[AW] = waddr_g_r1[AW];
    for(j=AW-1;j>0;j=j-1)begin
        waddr_r1[j ] = waddr_g_r1[j ] ^ waddr_r1 [j+1];
    end
end


//
///////////////////////////////////////////////////////////////
//read address

//========raddr+1========
reg  [AW:0] raddr;
wire [AW:0] raddrp1 = raddr + 1'b1;
always@(posedge clkout or negedge resetb)begin
    if(!resetb)
        raddr <= #ck2q 0;
    else if(oe) begin
        raddr <= #ck2q raddrp1;
    end
end

//========bcd to gray reg========
wire [AW:0] raddr_g;
assign      raddr_g[AW    ] = raddr[AW];
assign      raddr_g[AW-1:0] = raddr^raddr>>1;
reg  [AW:0] raddr_g_r0;
always@(posedge clkout or negedge resetb)begin
    if(!resetb)
        raddr_g_r0 <= #ck2q 0;
    else if(oe) begin
        raddr_g_r0 <= #ck2q raddr_g;
    end
end
//========rd_addr to wr domain========
reg  [AW:0] raddr_g_w0,raddr_g_w1;
always@(posedge clkin or negedge resetb)begin
    if(!resetb)begin
        raddr_g_w0 <= #ck2q 0;
        raddr_g_w1 <= #ck2q 0;
    end
    else begin
        raddr_g_w0 <= #ck2q raddr_g_r0;
        raddr_g_w1 <= #ck2q raddr_g_w0;
    end
end
//========gray to bcd======== 
reg [AW:0] raddr_w1;
integer i;
always@(raddr_g_w1)begin
       raddr_w1[AW] = raddr_g_w1[AW];
    for(i=AW-1;i>0;i=i-1)begin
       raddr_w1[i ] = radr_g_w1[i ] ^ raddr_w1[i+1];
    end
end


//
///////////////////////////////////////////////////////////////////
//

//=======wr_full//rd_empty====
assign wr_full  = ( wire_ie && !(waddr[AW]&&raddr_w1[AW]) && (waddr[AW-1:0]==raddr_w1[AW-1:0]) );
assign rd_empty = (             (raddr[AW]&&waddr_r1[AW]) && (raddr[AW-1:0]==waddr_r1[AW-1:0]) );

endmodule