lattice FPGA 官方的 ecp3 DEMO 在重新配合后会报错“Reference to undefined module ddr_pll ”，请问怎么解决？

lattice 官方的 ecp3 DEMO 在重新配合后会报错“Reference to undefined module ddr_pll ”，请问怎么解决？

错误内容如下：

ERROR – CG389 :”DK-ECP3-DDR3-011\core\ddr_p_eval\ddr3core\src\rtl\top\ecp3\ddr3_sdram_mem_top_wrapper.v”:200:8:200:17|Reference to undefined module ddr_pll

ERROR – CG389 :”DK-ECP3-DDR3-011\core\ddr_p_eval\ddr3core\src\rtl\top\ecp3\ddr3_sdram_mem_top_wrapper.v”:200:8:200:17|Illegal or Unsupported Syntax within black box. Use: // synthesis translate_off { unsupported Verilog } // synthesis translate_on

ERROR – CG389 :”DK-ECP3-DDR3-011\core\ddr_p_eval\ddr3core\src\rtl\top\ecp3\ddr3_sdram_mem_top_wrapper.v”:200:8:200:17|Alternatively, set the builtin compiler directive IGNORE_VERILOG_BLACKBOX_GUTS in the Verilog tab of the UI or set `define IGNORE_VERILOG_BLACKBOX_GUTS in any Verilog file.