1FPGA/IC优质开源项目(一)
-
Alexforencich系列
Verilog Ethernet Components
介绍
这个项目早在2021年就推荐过,只是当时简略的介绍了alexforencich网站而没有更详细的去介绍。
以太网组件,设计语言为Verilog,代码完全可见,并且提供Xilinx和Intel官方板子的例程。比如Xilinx Kintex 7 XC7K325T,Xilinx Artix 7 XC7A35T,Intel Cyclone 10 10CL025YU256I7G,Intel Cyclone IV E EP4CE115F29C7等等。可移植性高,通过上层的参数可配置为Xilinx的Vivado平台以及Intel的Quartus平台,大家不用过多担心因为平台的原因而需要做过多的修改,比如大家关心的Vivado和Quartus支持的一些iddr和oddr等核的不同,代码也通过参数化来进行设计,方便不同平台的移植。
支持1G/10G/25G速率。仅支持IP和ARP,使用的是ip_complete (1G) 或者ip_complete_64(10G/25G)。支持UDP,IP和ARP,使用udp_complete (1G) 或者udp_complete_64(10G/25G)。
源文件如下
rtl/arp.v : ARP handling logic rtl/arp_cache.v : ARP LRU cache rtl/arp_eth_rx.v : ARP frame receiver rtl/arp_eth_tx.v : ARP frame transmitter rtl/eth_arb_mux.py : Ethernet frame arbitrated multiplexer generator rtl/axis_eth_fcs.v : Ethernet FCS calculator rtl/axis_eth_fcs_64.v : Ethernet FCS calculator (64 bit) rtl/axis_eth_fcs_insert.v : Ethernet FCS inserter rtl/axis_eth_fcs_check.v : Ethernet FCS checker rtl/axis_gmii_rx.v : AXI stream GMII/MII receiver rtl/axis_gmii_tx.v : AXI stream GMII/MII transmitter rtl/axis_xgmii_rx_32.v : AXI stream XGMII receiver (32 bit) rtl/axis_xgmii_rx_64.v : AXI stream XGMII receiver (64 bit) rtl/axis_xgmii_tx_32.v : AXI stream XGMII transmitter (32 bit) rtl/axis_xgmii_tx_64.v : AXI stream XGMII transmitter (64 bit) rtl/eth_arb_mux.v : Ethernet frame arbitrated multiplexer rtl/eth_axis_rx.v : Ethernet frame receiver rtl/eth_axis_tx.v : Ethernet frame transmitter rtl/eth_demux.v : Ethernet frame demultiplexer rtl/eth_mac_1g.v : Gigabit Ethernet GMII MAC rtl/eth_mac_1g_fifo.v : Gigabit Ethernet GMII MAC with FIFO rtl/eth_mac_1g_gmii.v : Tri-mode Ethernet GMII/MII MAC rtl/eth_mac_1g_gmii_fifo.v : Tri-mode Ethernet GMII/MII MAC with FIFO rtl/eth_mac_1g_rgmii.v : Tri-mode Ethernet RGMII MAC rtl/eth_mac_1g_rgmii_fifo.v : Tri-mode Ethernet RGMII MAC with FIFO rtl/eth_mac_10g.v : 10G/25G Ethernet XGMII MAC rtl/eth_mac_10g_fifo.v : 10G/25G Ethernet XGMII MAC with FIFO rtl/eth_mac_mii.v : Ethernet MII MAC rtl/eth_mac_mii_fifo.v : Ethernet MII MAC with FIFO rtl/eth_mac_phy_10g.v : 10G/25G Ethernet XGMII MAC/PHY rtl/eth_mac_phy_10g_fifo.v : 10G/25G Ethernet XGMII MAC/PHY with FIFO rtl/eth_mac_phy_10g_rx.v : 10G/25G Ethernet XGMII MAC/PHY RX with FIFO rtl/eth_mac_phy_10g_tx.v : 10G/25G Ethernet XGMII MAC/PHY TX with FIFO rtl/eth_mux.v : Ethernet frame multiplexer rtl/gmii_phy_if.v : GMII PHY interface rtl/iddr.v : Generic DDR input register rtl/ip.v : IPv4 block rtl/ip_64.v : IPv4 block (64 bit) rtl/ip_arb_mux.v : IP frame arbitrated multiplexer rtl/ip_complete.v : IPv4 stack (IP-ARP integration) rtl/ip_complete_64.v : IPv4 stack (IP-ARP integration) (64 bit) rtl/ip_demux.v : IP frame demultiplexer rtl/ip_eth_rx.v : IPv4 frame receiver rtl/ip_eth_rx_64.v : IPv4 frame receiver (64 bit) rtl/ip_eth_tx.v : IPv4 frame transmitter rtl/ip_eth_tx_64.v : IPv4 frame transmitter (64 bit) rtl/ip_mux.v : IP frame multiplexer rtl/lfsr.v : Generic LFSR/CRC module rtl/mii_phy_if.v : MII PHY interface rtl/oddr.v : Generic DDR output register rtl/ptp_clock.v : PTP clock rtl/ptp_clock_cdc.v : PTP clock CDC rtl/ptp_ts_extract.v : PTP timestamp extract rtl/ptp_perout.v : PTP period out rtl/rgmii_phy_if.v : RGMII PHY interface rtl/ssio_ddr_in.v : Generic source synchronous IO DDR input module rtl/ssio_ddr_in_diff.v : Generic source synchronous IO DDR differential input module rtl/ssio_ddr_out.v : Generic source synchronous IO DDR output module rtl/ssio_ddr_out_diff.v : Generic source synchronous IO DDR differential output module rtl/ssio_sdr_in.v : Generic source synchronous IO SDR input module rtl/ssio_sdr_in_diff.v : Generic source synchronous IO SDR differential input module rtl/ssio_sdr_out.v : Generic source synchronous IO SDR output module rtl/ssio_sdr_out_diff.v : Generic source synchronous IO SDR differential output module rtl/udp.v : UDP block rtl/udp_64.v : UDP block (64 bit) rtl/udp_arb_mux.v : UDP frame arbitrated multiplexer rtl/udp_checksum_gen.v : UDP checksum generator rtl/udp_checksum_gen_64.v : UDP checksum generator (64 bit) rtl/udp_complete.v : UDP stack (IP-ARP-UDP) rtl/udp_complete_64.v : UDP stack (IP-ARP-UDP) (64 bit) rtl/udp_demux.v : UDP frame demultiplexer rtl/udp_ip_rx.v : UDP frame receiver rtl/udp_ip_rx_64.v : UDP frame receiver (64 bit) rtl/udp_ip_tx.v : UDP frame transmitter rtl/udp_ip_tx_64.v : UDP frame transmitter (64 bit) rtl/udp_mux.v : UDP frame multiplexer rtl/xgmii_baser_dec_64.v : XGMII 10GBASE-R decoder rtl/xgmii_baser_enc_64.v : XGMII 10GBASE-R encoder rtl/xgmii_deinterleave.v : XGMII data/control de-interleaver rtl/xgmii_interleave.v : XGMII data/control interleaver
示例
以项目提供的K705为例,支持gmii,rgmii以及sgmii接口,可以通过makefile恢复工程。受限于硬件条件,我没有上板测试,官方提供了完整的测试文件,是可以跑通的,这里我仅贴上Vivado的综合图片,对以太网感兴趣的朋友可以自己进一步的测试。(下图是rgmii综合出的原理图)
开源地址
// github地址 https://github.com/alexforencich/verilog-ethernet.git // 官网地址 http://alexforencich.com/wiki/en/verilog/ethernet/start
没有回复内容