运行Diamond 3.1 Translate Design出现 “there is no active CLK. ” 错误怎么解决？

在Diamond 3.1运行过程中出现了如下问题，在Spreadsheet View界面中有两个信号显示unconnected，运行Diamond 3.1 Translate Design，会有如下两个告警和错误。

WARNING – logical net ‘BRDWR’ has no load.
WARNING – logical net ‘BDOUT’ has no load.
ERROR – Port ‘BDOUT’ is unconnected.
ERROR – Port ‘BRDWR’ is unconnected.

以BDOUT为例，代码中对BDOUT（内部模块信号名为bd_out_in，接口名为BDOUT）做了如下处理：

always@(posedge data_clk or posedge pwr_rst) 
        begin 
        if(pwr_rst==1'b1) 
                begin 
                  din[15:0]     <= 16'b0; 
                end 
      else 
            begin 
                din[15:0]     <= {din[14:0],bd_out_in}; 
            end 
      end

运行Place&Route Design时，会出现如下错误：

71031171 ERROR – blockcheck: in SLICE u_ads8320e_if/u2_ram_64x16/mem_3_7/SLICE_12, WCLKMUX select CLKMUX but there is no active CLK.

请各位帮忙解答一下，非常感谢！