赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。在第90页，介绍了此IP核的结构，示意图如下：

User interface block

User interface block 简称为UI block

User interface

这里面的接口

User Interface Block and User Interface

The UI block presents the UI to the user FPGA logic block. It provides a simple alternative to

the native interface by presenting a flat address space and buffering read and write data.

 

UI block的各个接口定义：

app_addr[ADDR_WIDTH – 1:0]

此输入指的是提交给UI模块的要求信号的地址。UI模块聚合外部SDRAM的所有地址字段，并向用户提供平面地址空间。

（我的注释平面地址空间：内存地址采用线性连续编址形成的空间。）

app_cmd[2:0]

此输入指的是提交给UI模块的要求信号的命令。命令的具体信息见下：

Operation工作模式	app_cmd[2:0] Code
Read读	001
Write写	000

app_en

此输入使能一次请求。（This input strobes in a request.）使用时，必须线给定  app_addr[],

app_cmd[2:0],和app_hi_pri的值,再把 app_en 置1，这样提交UI模块这次申请。UI模块表明已收到，把app_rdy置1，完成一次握手。（This initiates a handshake that the UI acknowledges by asserting app_rdy.）

app_hi_pri

This input indicates that the current request is a high priority.

此输入表明当前的请求是高优先级的。

app_wdf_data[APP_DATA_WIDTH – 1:0]

This bus provides the data currently being written to the external memory.

这条总线提供当前写入外部存储器的数据。

我的注释：

Rank 是可以单独寻址的一组dram

搜索ddr rank 查到 8个内存颗粒（每个颗粒位宽8bit）并联起来 形成给cpu的数据64bit，64bit是rank

 

app_wdf_end

This input indicates that the data on the app_wdf_data[] bus in the current cycle is the

last data for the current request.

该输入表示当前周期内app_wdf_data []总线上的数据为当前请求的最后数据。

app_wdf_mask[APP_MASK_WIDTH – 1:0] 我估计APP_MASK_WIDTH=32 因为data是256宽度

This bus indicates which bytes of app_wdf_data[] are written to the external memory and

which bytes remain in their current state. The bytes are masked by setting a value of 1 to the

corresponding bits in app_wdf_mask. For example, if the application data width is 256, the

mask width takes a value of 32. The least significant byte [7:0] of app_wdf_data is masked

using Bit[0] of app_wdf_mask and the most significant byte [255:248] of app_wdf_data

is masked using Bit[31] of app_wdf_mask. Hence if you have to mask the last DWORD, that

is, bytes 0, 1, 2, and 3 of app_wdf_data, the app_wdf_mask should be set to

32’h0000_000F.

该总线指示哪些字节的app_wdf_data []数据被写入外部内存，以及哪些字节保持其当前状态。app_wdf_mask中的设置为1的位表示对应的字节被掩码。例如，如果应用数据（app_wdf_data）的宽度为256，则app_wdf_mask的宽度为32。最低字节app_wdf_data [7:0]用app_wdf_mask[0]来表示掩码，最高字节[255:248] 用app_wdf_mask[31]来表示掩码。如果需要掩码最低字（最低四字节），则app_wdf_mask的值应设置为32’h0000_000F.

app_wdf_wren

This input indicates that the data on the app_wdf_data[] bus is valid.

该输入表示 app_wdf_data []总线上的数据有效。

app_rdy

This output indicates to you whether the request currently being submitted to the UI is

accepted. If the UI does not assert this signal after app_en is asserted, the current request

must be retried. The app_rdy output is not asserted if:

° PHY/Memory initialization is not yet completed

° All the bank machines are occupied (can be viewed as the command buffer being

full)

– A read is requested and the read buffer is full

– A write is requested and no write buffer pointers are available

° A periodic read is being inserted

该输出表示现在可以向UI模块提交（读）请求。如果app_en为1之后，UI模块没有把app_rdy

置1，需要重试。如果出现以下情况，app_rdy不会被置1：

1）物理层/内存初始化尚未完成

2）所有bank machines都被占用（可以视为命令缓冲区被占满）

——有读取请求，并且读取缓冲区已满。

——有写入请求，但没有可用的写入缓冲区指针

3）正在插入定期读取

app_rd_data[APP_DATA_WIDTH – 1:0]

This output contains the data read from the external memory.

该输出包含从外部存储器读取的数据。

app_rd_data_end

This output indicates that the data on the app_rd_data[] bus in the current cycle is the

last data for the current request.

该输出表明当前周期中app_rd_data []总线上的数据是当前请求的最后数据。

app_rd_data_valid

This output indicates that the data on the app_rd_data[] bus is valid.

该输出表明app_rd_data []总线上的数据有效。

app_wdf_rdy

This output indicates that the write data FIFO is ready to receive data. Write data is accepted

when both app_wdf_rdy and app_wdf_wren are asserted.

当app_wdf_rdy和app_wdf_wren均被置1时，该输出表明write data FIFO已准备好接收数据。

app_ref_req

When asserted, this active-High input requests that the Memory Controller send a refresh

command to the DRAM. It must be pulsed for a single cycle to make the request and then

deasserted at least until the app_ref_ack signal is asserted to acknowledge the request

and indicate that it has been sent.

当此高有效输入被置1时，表示内存控制器（Memory Controller）向DRAM发送一个刷新指令。它必须保持一个周期的脉冲才能确认本次请求，然后至少在app_ref_ack信号被置1以确认请求之后，才能置0，表明已发送完成。

app_ref_ack

When asserted, this active-High input acknowledges a refresh request and indicates that

the command has been sent from the Memory Controller to the PHY.

当此高有效输入被置1时，确认了刷新请求，并表示该命令已从内存控制器（Memory Controller）发送到物理层。

app_zq_req

When asserted, this active-High input requests that the Memory Controller send a ZQ

calibration command to the DRAM. It must be pulsed for a single cycle to make the request

and then deasserted at least until the app_zq_ack signal is asserted to acknowledge the

request and indicate that it has been sent.

当此高有效输入被置1时，表明内存控制器发送ZQ校准命令给DRAM。它必须保持一个脉冲周期才能确认这个请求，然后至少在app_zq_ack信号被置1以确认请求之后，才能置0，表明已发送完成。

app_zq_ack

When asserted, this active-High input acknowledges a ZQ calibration request and indicates

that the command has been sent from the Memory Controller to the PHY

当此高有效输入被置1时，表明确认ZQ校准请求，并表示该命令已从内存控制器发送到物理层。

ui_clk_sync_rst

This is the reset from the UI which is in synchronous with ui_clk.

这是从UI模块来的复位，与 ui_clk同步。

ui_clk

This is the output clock from the UI. It must be a half or quarter the frequency of the clock

going out to the external SDRAM, which depends on 2:1 or 4:1 mode selected in GUI.

这是UI模块的输出时钟。它必须是连接外部SDRAM时钟频率的一半或四分之一，具体是哪种取决于GUI中选择的2:1或4:1模式。

init_calib_complete

The PHY asserts init_calib_complete when calibration is finished. The application has

no need to wait for init_calib_complete before sending commands to the Memory

Controller