赛灵思的DDR IP手册ug586翻译和学习（2）第二章 AXI4 slave interface block AXI4从设备接口模块

赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继续上一篇，翻译和学习的是AXI4 Slave Interface Block，也就是AXI4从设备接口模块。

The AXI4 slave interface block maps AXI4 transactions to the UI interface to provide an industry-standard bus protocol interface to the Memory Controller. The AXI4 slave interface is optional in designs provided through the MIG tool. The RTL is consistent between both tools. For details on the AXI4 signaling protocol, see the Arm AMBA specifications [Ref 4].

AXI4从设备接口模块将AXI4事务映射到UI接口，以提供内存控制器（Memory Controller）的工业标准总线协议接口。AXI4从设备接口在设计中是可选的，通过MIG工具选择。

在。RTL在两种工具之间是一致的。有关AXI4信号协议的详细信息，请参阅Arm AMBA规范[Ref 4]。

The overall design is composed of separate blocks to handle each AXI channel, which allows

for independent read and write transactions. Read and write commands to the UI rely on a

simple round-robin arbiter to handle simultaneous requests. The address read/address

write modules are responsible for chopping the AXI4 burst/wrap requests into smaller

memory size burst lengths of either four or eight, and also conveying the smaller burst

lengths to the read/write data modules so they can interact with the user interface.

整体设计由不同的AXI 通道模块组成，每个AXI通道有独立的读写事务。给UI模块的读写命令用简单 round-robin仲裁器进行同时发生的请求仲裁。地址读取/地址写入模块负责将AXI4 burst/wrap的请求分解为较小的内存大小突发长度（长度为4或8），也传输更小的burst读取/写入数据模块的长度给读写数据模块（read/write data modules），以便它们可以与UI交互。

If ECC is enabled, all write commands with any of the mask bits enabled are issued as

read-modify-write operation.

If ECC is enabled, all write commands with none of the mask bits enabled are issued as write

operation.

如果启用ECC，则所有启用任何掩码位的写命令都将作为read-modify-write操作。

如果启用ECC，则所有未启用掩码位的写命令都将作为写命令发出。

以下略去两个表

AXI4从接口参数 和 AXI从接口信号定义

Arbitration in AXI Shim

The AXI4 protocol calls for independent read and write address channels. The Memory Controller has one address channel. The following arbitration options are available for arbitrating between the read and write address channels.

AXI Shim中的仲裁

AXI4协议需要独立的读写地址通道。内存控制器（Memory Controller）有一个地址通道。以下仲裁选项适用于在读和写地址通道之间进行仲裁。

Time Division Multiplexing (TDM)

Equal priority is given to read and write address channels in this mode. The grant to the read and write address channels alternate every clock cycle. The read or write requests from the AXI master has no bearing on the grants. For example, the read requests are served in alternative clock cycles, even when there are no write requests. The slots are fixed and they are served in their respective slots only.

时分多路复用（TDM）

在这种模式下，读取和写入地址通道具有同等的优先级。读和写地址通道的准许接通（grant）在每个时钟周期交替。来自AXI主设备的读或写请求与准许接通（grant）无关。例如，读取请求在每隔一个时钟周期出现一次，即使没有写请求。读、写时隙（slot）是固定的，仅在各自分配到的时隙中提供。

Round-Robin

Equal priority is given to read and write address channels in this mode. The grant to the read and write channels depends on the last served request granted from the AXI master.

For example, if the last performed operation is write, then it gives precedence for read operation to be served over write operation. Similarly, if the last performed operation is read, then it gives precedence for write operation to be served over read operation. If both read and write channels requests at the same time when there are no pending requests, this scheme serves write channel ahead of read.

Round-Robin模式

在这种模式下，读取和写入地址通道具有同等的优先级。读和写地址通道的准许接通（grant）取决于来自之前最后一次AXI主设备的请求。

例如，如果最后执行的操作是写操作，则它为读操作提供优先权。类似地，如果最后执行的操作是读取，则它使写入操作优先于读取操作。如果没有挂起的请求时读写通道请求同时发生的时候，它使写优先于读。

Read Priority (RD_PRI_REG)

Read and write address channels are served with equal priority in this mode. The requests

from the write address channel are processed when one of the following occurs:

• No pending requests from read address channel.

• Read starve limit of 256 is reached. It is only checked at the end of the burst.

• Read wait limit of 16 is reached.

• Write QOS is higher which is non-zero. It is only checked at the end of the burst.

The requests from the read address channel are processed in a similar method.

Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT)

The read address channel is always given priority in this mode. The requests from the write

address channel are processed when there are no pending requests from the read address

channel or the starve limit for read is reached.