赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继续上一篇，翻译和学习的是Memory Controller，也就是内存控制器模块。
Memory Controller
In the core default configuration, the Memory Controller (MC) resides between the UI block and the physical layer. This is depicted in Figure 1-53
在IP核的默认配置中，内存控制器（MC）位于UI模块和物理层之间。如图1-53所示
（我注释：从Bank Machines到Precharge Policy 属于MC模块）
The Memory Controller is the primary logic block of the memory interface. The Memory Controller receives requests from the UI and stores them in a logical queue. Requests are optionally reordered to optimize system throughput and latency.
The Memory Controller block is organized as four main pieces:
• A configurable number of “bank machines”
• A configurable number of “rank machines”
• A column machine
• An arbitration block
内存控制器是内存接口的主要逻辑块。内存控制器接收来自UI模块的请求，并将其存储在逻辑队列中。请求可以选择性地重新排序，以优化系统吞吐量和延迟。
内存控制器块由四个主要部分组成：
•可配置数量的“bank machines”
•可配置数量的“rank machines”
•一个列machine
•一个仲裁模块
Bank Machines
Most of the Memory Controller logic resides in the bank machines. Bank machines correspond to DRAM banks. A given bank machine manages a single DRAM bank at any given time. However, bank machine assignment is dynamic, so it is not necessary to have a bank machine for each physical bank. The number of banks can be configured to trade off between area and performance. This is discussed in greater detail in the Precharge Policy section.
大多数内存控制器逻辑驻留在bank machines中。bank machines对应于DRAM的bank。给定的bank machines在任何给定时间内管理单个DRAM bank。然而，bank machines分配是动态的，因此没有必要为每个物理bank都配备bank machines。bank数量可以在面积和性能之间进行权衡。预充电策略部分对此进行了更详细的讨论。
The duration of a bank machine assignment to a particular DRAM bank is coupled to user requests rather than the state of the target DRAM bank. When a request is accepted, it is assigned to a bank machine. When a request is complete, the bank machine is released and is made available for assignment to another request. Bank machines issue all the commands necessary to complete the request.
bank machine分配给特定DRAM bank的持续时间与用户请求相一致，而不是与目标DRAM bank 的状态相一致。当请求被接受时，它被分配给bank machine。当一个请求完成时，bank machine被释放，并可分配给另一个请求。bank machine发出完成请求所需的所有命令。
On behalf of the current request, a bank machine must generate row commands and column commands to complete the request. Row and column commands are independent but must adhere to DRAM timing requirements.
The following example illustrates this concept. Consider the case when the Memory Controller and DRAM are idle when a single request arrives. The bank machine at the head of the pool:
1. Accepts your request
2. Activates the target row
3. Issues the column (read or write) command
4. Precharges the target row
5. Returns to the idle pool of bank machines
代表当前请求，bank machine必须生成行命令和列命令以完成请求。行和列命令是独立的，但必须符合DRAM时序要求。
下面的示例说明了这个概念。该例子是当单个请求到达时，内存控制器和DRAM处于空闲的情况。bank machine在pool的开头：
1、接受您的请求
2、激活目标行
3、发出列（读或写）命令
4、对目标行预充电Precharges
5、返回bank machines空闲池pool
Similar functionality applies when multiple requests arrive targeting different rows or banks.
Now consider the case when a request arrives targeting an open DRAM bank, managed by an already active bank machine. The already active bank machine recognizes that the new request targets the same DRAM bank and skips the precharge step (step 4). The bank machine at the head of the idle pool accepts the new user request and skips the activate step (step 2).
类似的功能适用于多个针对不同行或bank的请求到达时。
现在考虑当一个请求到达一个开放的DRAM bank时的情况，该bank由一个已经激活的bank machine管理。已激活的bank machine识别出针对同一DRAM bank的新请求，并跳过预充电步骤precharge step（步骤4）。空闲池开头的bank machine可以接受新用户请求并跳过激活步骤（步骤2）。
Finally, when a request arrives in between both a previous and subsequent request all to the same target DRAM bank, the controller skips both the activate (step 2) and precharge (step 4) operations.
A bank machine precharges a DRAM bank as soon as possible unless another pending request targets the same bank. This is discussed in greater detail in the Precharge Policy section.
最后，到达同一目标DRAM bank，并夹在前一个和后一个请求之间的一个请求到达时，控制器跳过激活（步骤2）和预充电（步骤4）操作。
除非有针对同一bank的另一个未决请求来，否则bank machine尽快对DRAM bank预充电。预充电政策部分对此进行了更详细的讨论。
Column commands can be reordered for the purpose of optimizing memory interface throughput. The ordering algorithm nominally ensures data coherence. The reordering feature is explained in greater detail in the Reordering section.
为了优化内存接口吞吐量，可以对列命令重新排序。排序算法名义上确保了数据的一致性。重新排序部分将更详细地解释重新排序功能。
Rank Machines
The rank machines correspond to DRAM ranks. Rank machines monitor the activity of the bank machines and track rank or device-specific timing parameters. For example, a rank machine monitors the number of activate commands sent to a rank within a time window.
After the allowed number of activates have been sent, the rank machine generates an inhibit signal that prevents the bank machines from sending any further activates to the rank until the time window has shifted enough to allow more activates. Rank machines are statically assigned to a physical DRAM rank.
rank machines
rank machines对应于DRAM 的rank。rank machines监视着bank machines的行为,并跟踪rank 或着设备特定的时间参数。例如，rank machines监控在某时间窗口内发送到rank的激活命令的数量。
发送允许的激活次数后，rank machines生成抑制信号，在时间窗口移动到足以允许更多激活之前，防止bank machines向rank发送更多的激活指令。Rank machines静态分配给物理DRAM的rank。
Column Machine
The single column machine generates the timing information necessary to manage the DQ data bus. Although there can be multiple DRAM ranks, because there is a single DQ bus, all the columns in all DRAM ranks are managed as a single unit. The column machine monitors commands issued by the bank machines and generates inhibit signals back to the bank machines so that the DQ bus is utilized in an orderly manner.
列machine
单列machine生成管理DQ数据总线所需的时序信息。虽然可以有多个DRAM ranks，但由于存在单个DQ总线，所有DRAM列中的所有列都作为单个单元进行管理。列machine监控bank machines发出的命令，并生成返回bank machines的抑制信号，以便有序地使用DQ总线。
Arbitration Block
The arbitration block receives requests to send commands to the DRAM array from the bank machines. Row commands and column commands are arbitrated independently. For each command opportunity, the arbiter block selects a row and a column command to forward to the physical layer. The arbitration block implements a round-robin protocol to ensure forward progress.
仲裁模块
仲裁模块从bank machines接收向DRAM阵列发送命令的请求。行命令和列命令是独立仲裁的。对于每个命令，仲裁模块选择一行和一列命令转发到物理层。仲裁块实现了一个round-robin协议，以确保向前进行（forward progress）.。
Reordering
DRAM accesses are broken into two quasi-independent parts, row commands and column commands. Each request occupies a logical queue entry, and each queue entry has an associated bank machine. These bank machines track the state of the DRAM rank or bank it is currently bound to, if any.
重新排序
DRAM访问分为两个准独立的部分，行命令和列命令。每个请求占用一个逻辑队列条目，每个队列条目都有一个关联的bank machines。这些bank machines跟踪其当前绑定到的DRAM列或bank（如果有）的状态。
If necessary, the bank machine attempts to activate the proper rank, bank, or row on behalf of the current request. In the process of doing so, the bank machine looks at the current state of the DRAM to decide if various timing parameters are met. Eventually, all timing parameters are met and the bank machine arbitrates to send the activate. The arbitration is done in a simple round-robin manner. Arbitration is necessary because several bank machines might request to send row commands (activate and precharge) at the same time.
如有必要，bank machine将尝试代表当前请求激活适当的rank、bank或行。在此过程中，bank machine查看DRAM的当前状态，以确定是否满足各种定时参数。最终，所有定时参数都被满足，bank machine进行仲裁以发送激活。仲裁以简单的round-robin循环方式进行。仲裁是必要的，因为多台bank machine可能同时请求发送行命令（激活和预充电）。
Not all requests require an activate. If a preceding request has activated the same rank, bank, or row, a subsequent request might inherit the bank machine state and avoid the precharge/activate penalties.
并非所有请求都需要激活。如果之前的请求激活了相同的rank、bank或行，则后续请求可能会继承bank machine状态，并避免预充电/激活惩罚。
After the necessary rank, bank, or row is activated and the RAS to CAS delay timing is met, the bank machine tries to issue the CAS-READ or CAS-WRITE command. Unlike the row command, all requests issue a CAS command. Before arbitrating to send a CAS command, the bank machine must look at the state of the DRAM, the state of the DQ bus, priority, and ordering. Eventually, all these factors assume their favorable states and the bank machine arbitrates to send a CAS command. In a manner similar to row commands, a round-robin arbiter uses a priority scheme and selects the next column command.
在激活必要的rank、列或行并且满足RAS到CAS延迟定时后，bank machine尝试发出CAS-READ或CAS-WRITE命令。与row命令不同，所有请求都发出CAS命令。在仲裁发送CAS命令之前，bank machine必须查看DRAM的状态、DQ总线的状态、优先级和顺序。最终，所有这些因素都假设它们处于有利状态，bank machine进行仲裁以发送CAS命令。与row命令类似，round-robin循环仲裁器使用优先级方案并选择下一个列命令。
The round-robin arbiter itself is a source of reordering. Assume for example that an otherwise idle Memory Controller receives a burst of new requests while processing a refresh. These requests queue up and wait for the refresh to complete. After the DRAM is ready to receive a new activate, all waiting requests assert their arbitration requests simultaneously. The arbiter selects the next activate to send based solely on its round-robin algorithm, independent of request order. Similar behavior can be observed for column commands.
round-robin循环仲裁器本身就是重新排序的来源。例如，假设一个空闲的内存控制器在处理刷新时接收到一系列新请求。这些请求排队等待刷新完成。DRAM准备好接收新激活后，所有等待的请求同时声明其仲裁请求。仲裁器仅根据其循环算法选择下一个要发送的激活，与请求顺序无关。可以观察到列命令的类似行为。
The controller supports three ordering modes:
• STRICT – In this mode the controller always issues commands to the memory in the exact order received at the native interface. This mode can be useful in situations that do not benefit from reordering and the lowest latency is desired. Because the read data comes back in order, the user interface layer might not be needed thus reducing latency. This mode is also useful for debugging.
控制器支持三种命令模式：
•严格–在这种模式下，控制器总是按照本机接口接收到的确切顺序向内存发出命令。此模式在不受益于重新排序且需要最低延迟的情况下非常有用。由于读取的数据按顺序返回，因此可能不需要用户界面（）UI层，从而减少延迟。此模式对于调试也很有用。
• NORM – In this mode the controller reorders reads but not writes as needed to improve efficiency. All write requests are issued in the request order relative to all other write requests, and requests within a given rank-bank retire in order. This ensures that it is not possible to observe the result of a later write before an earlier write completes.
Note: This reordering is only visible at the native interface. The user interface reorders the read requests back into the original request order.
•NORM–在此模式下，控制器会重新排序读取，但不重新排序写入，以提高效率（读可以重新排序，写不用，因为写有固定的顺序）。相对于所有其他写请求，所有写请求都按请求顺序发出，并且给定rank-bank中的请求按顺序失效。这确保了在前一次写入完成之前，不可能观察到后一次写入的结果。
注意：这种重新排序仅在native interface上可见。用户界面(UI)将读取请求重新排序为原始请求顺序。
• RELAXED – This is the most efficient mode of the controller. Writes and reads can be reordered as needed for maximum efficiency between rank-bank queues. Thus in this mode it is possible to observe the reordering of writes. However, this behavior is not observable at the user interface layer because the requests are retired in order within a rank-bank and the user interface layer returns the read requests in order. Therefore the RELAXED mode is recommended for use with the user interface layer.
•放松-这是控制器最有效的模式。可以根据需要对写入和读取进行重新排序，以在rank-bank队列之间实现最大效率。因此，在此模式下，可以观察写入的重新排序。然而，这种行为在用户界面层(UI)是不可见的，因为请求在rank-bank中按顺序失效，并且用户界面层按顺序返回读取请求。因此，建议(mc模块)与用户界面层（UI模块）一起使用放松模式。
Note: This option is not selectable in the MIG GUI. To enable, generate the design with the synthesis options “Global” in the Generate Output Products settings. After generating the design, the design top-level RTL file should be edited and the ORDERING parameter should be changed to “RELAXED.”
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