赛灵思的DDR IP手册ug586翻译和学习（4）第四章 User Interface的使用方式

赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继

续上一篇，翻译和学习的是User Interface的使用方式，也就是用户接口模块的使用方式。

The mapping between the User Interface address bus and the physical memory row, bank and column can be configured. Depending on how the application data is organized, addressing scheme Bank- Row-Column or Row-Bank-Column can be chosen to optimize controller efficiency. These addressing schemes are shown in Figure 1-72 and Figure 1-73

用户界面UI

可以配置用户界面地址总线和物理内存行、bank和列之间的映射。根据应用程序数据的组织方式，可以选择寻址方案bank-行–列或行-bank-列来优化控制器效率。这些寻址方案如图1-72和图1-73所示

Figure 1-72: Memory Address Mapping for Bank-Row-Column Mode in UI Module

Figure 1-73: Memory Address Mapping for Row-Bank-Column Mode in UI Module

Figure 1-72 and Figure 1-73 show that the address map is controlled by the string parameter MEM_ADDR_ORDER. This parameter can take the following values:

• BANK_ROW_COLUMN – Address map is as shown in Figure 1-72.

• ROW_BANK_COLUMN – Address map is as shown in Figure 1-73.

• TG_TEST – Address map is used for testing purpose only. It enables the address remap to test address access to different portions of the DRAM. It remaps the address as explained in the following examples. The remap is done within the UI portion of the controller.

Note: The row width, column width, and bank width value settings are assumed for the following examples:

° Row Width – 15

° Bank Width – 3

° Column Width – 10

Example (1) – When the selected option in the MIG GUI is BANK_ROW_COLUMN and the address to the controller is mapped accordingly.

图1-72和图1-73显示，地址映射由字符串参数MEM_ADDR_ORDER控制。此参数可以采用以下值：

•BANK_ROW_COLUMN–地址图如图1-72所示。

•ROW_BANK_COLUMN–地址图如图1-73所示。

•TG_TEST–地址映射仅用于测试目的。它使地址重新映射能够测试对DRAM不同部分的地址访问。它重新映射地址，如以下示例中所述。重新映射在控制器的UI部分内完成。

注意：对于以下示例，假设行宽度、列宽和bank宽度值设置：

°行宽–15

°bank宽度–3

°列宽–10

示例（1）–当MIG GUI中的选定选项为BANK_ROW_COLUMN，并且控制器的地址相应映射时。

Example (1) – When the selected option in the MIG GUI is BANK_ROW_COLUMN and the

address to the controller is mapped accordingly.

Example (2) – When the selected option in the MIG GUI is ROW_BANK_COLUMN and the

address to the controller is mapped accordingly.

示例（2）–当MIG GUI中的选定选项为BANK_ROW_COLOMN，并且控制器的地址相应映射时。

Command Path

When the user logic app_en signal is asserted and the app_rdy signal is asserted from the UI, a command is accepted and written to the FIFO by the UI. The command is ignored by the UI whenever app_rdy is deasserted. The user logic needs to hold app_en High along with the valid command and address values until app_rdy is asserted as shown in

Figure 1-74.

命令路径

当用户逻辑app_en信号=1并且app_rdy信号被UI设为1时，UI接受命令并将其写入FIFO。每当app_rdy=0时，UI就会忽略该命令。用户逻辑需要将app_en以及有效的命令和地址值保持在高位，直到app_rdy=1，如图1-74所示。

A non back-to-back write command can be issued as shown in Figure 1-75. This figure depicts three scenarios for the app_wdf_data, app_wdf_wren, and app_wdf_end signals, as follows:

1. Write data is presented along with the corresponding write command (second half of BL8).

2. Write data is presented before the corresponding write command.

3. Write data is presented after the corresponding write command, but should not exceed the limitation of two clock cycles.

For write data that is output after the write command has been registered, as shown in Note 3, the maximum delay is two clock cycles.

可以发出非背靠背写命令，如图1-75所示。该图描述了app_wdf_data, app_wdf_wren, and app_wdf_end信号的三种场景，如下所示：

对于写入命令注册后输出的写入数据，如注释3所示，最大延迟为两个时钟周期。

Write Path

The write data is registered in the write FIFO when app_wdf_wren is asserted and app_wdf_rdy is High (Figure 1-76). If app_wdf_rdy is deasserted, the user logic needs to hold app_wdf_wren and app_wdf_end High along with the valid app_wdf_data value until app_wdf_rdy is asserted. app_wdf_data data can be pushed even before app_cmd “write command” is asserted. The only condition is that for every app_cmd “write command,” the associated app_wdf_data “write data” must be present. The app_wdf_mask signal can be used to mask out the bytes to write to external memory.

写入路径

当app_wdf_wren=1时，app_wdf_rdy=1时，写入数据在写入FIFO中注册（图1-76）。如果app_wdf_rdy=0，则用户逻辑需要让app_wdf_wren和app_wdf_end保持为1与有效的app_wdf_data数据值一起保持高位直到app_wdf_rdy是1。（这一句还要仔细分析）

app_wdf_data数据甚至可以在app_cmd  “write command”=1之前推送。唯一要考虑的是每一个app_cmd  “write command”它相关的app_wdf_data “write data”必须存在。在写外部存储器的时候，app_wdf_mask信号可以用来屏蔽掉某些字节。

As shown in Figure 1-75, page 168, the maximum delay for a single write between the write data and the associated write command is two clock cycles.

The app_wdf_end signal must be used to indicate the end of a memory write burst. For memory burst types of eight in 2:1 mode, the app_wdf_end signal must be asserted on the second write data word.

The map of the application interface data to the DRAM output data can be explained with an example.

For a 4:1 Memory Controller to DRAM clock ratio with an 8-bit memory, at the application interface, if the 64-bit data driven is 0000_0806_0000_0805 (Hex), the data at the DRAM interface is as shown in Figure 1-78. This is for a Burst Length 8 (BL8) transaction.

如第168页图1-75所示，写入数据和它相关的写入命令之间的单次写入的最大延迟为两个时钟周期。

app_wdf_end信号必须用于指示内存写入突发的结束。对于2:1模式下的内存突发类型为8，必须在第二个写入数据字上app_wdf_end=1。

应用接口数据到DRAM输出数据的映射可以用示例来解释。

对于具有8位的4:1内存控制器与DRAM时钟比的内存，在应用程序接口处，如果驱动的64位数据为0000_0806_0000_0805（十六进制），则DRAM接口处的数据如图1-78所示。这适用于突发长度8（BL8）事务。

The data values at different clock edges are as shown in Table 1-63.

For a 2:1 Memory Controller to DRAM clock ratio, the application data width is 32 bits.

Hence for BL8 transactions, the data at the application interface must be provided in two clock cycles. The app_wdf_end signal is asserted for the second data as shown in Figure 1-79. In this case, the application data provided in the first cycle is 0000_0405 (Hex), and the data provided in the last cycle is 0000_080A (Hex). This is for a BL8 transaction.

Figure 1-80 shows the corresponding data at the DRAM interface.

Figure 1-80: Data at the DRAM Interface for 2:1 Mode.

不同时钟边缘的数据值如表1-63所示。

对于2:1的内存控制器与DRAM时钟比，application数据宽度为32位。

因此，对于BL8型传输，application接口上的数据必须在两个时钟周期内提供。如图1-79所示，第二个数据的时候app_wdf_end信号置1。在这种情况下，第一个周期中提供的应用数据是0000_0405（十六进制），最后一个周期中提供的数据是0000_080A（十六进制）。这适用于BL8型传输。

图1-80显示了DRAM界面上的相应数据。

图1-80:2:1模式下DRAM接口处的数据。

Read Path

The read data is returned by the UI in the requested order and is valid when app_rd_data_valid is asserted (Figure 1-81 and Figure 1-82). The app_rd_data_end signal indicates the end of each read command burst and is not needed in user logic.

In Figure 1-82, the read data returned is always in the same order as the requests made on the address/control bus.

读取路径

UI按请求的顺序返回读取的数据，当app_rd_data_valid=1时，读取的数据有效（图1-81和图1-82）。app_rd_data_end信号表示每个读取命令突发的结束，在用户逻辑中不需要。

在图1-82中，返回的读取数据的顺序始终与地址/控制总线上的请求相同。

User Refresh

For user-controlled refresh, the Memory Controller managed maintenance should be disabled by setting the USER_REFRESH parameter to “ON.”

To request a REF command, app_ref_req is strobed for one cycle. When the Memory Controller sends the command to the PHY, it strobes app_ref_ack for one cycle, after which another request can be sent. Figure 1-83 illustrates the interface.

用户刷新

对于用户控制的刷新，应通过将USER_REFRESH参数设置为“ON”来禁用内存控制器管理的维护

为了发出REF命令，将app_ref_req选通一个周期。当内存控制器将命令发送到PHY时，它将选通app_ref_ack 一个周期，然后可以发送另一个请求。图1-83说明了这个接口。

A user-refresh operation can be performed any time provided the handshake defined above is followed. There are no additional interfacing requirements with respect to other commands. However, pending requests affect when the operation goes out. The Memory Controller fulfills all pending data requests before issuing the refresh command. Timing parameters must be considered for each pending request when determining when to strobe app_ref_req to avoid a tREFI violation. To account for the worst case, subtract tRCD, CL, the data transit time, and tRP for each bank machine to ensure that all transactions can complete before tREFI expires. Equation 1-1 shows the REF request interval maximum.

遵循上面定义的握手出现，就可以随时执行用户刷新操作。对于其他命令，没有额外的接口要求。但是，挂起的请求会影响操作何时停止。内存控制器在发出刷新命令之前要完成所有挂起的数据请求。在确定何时选通app_ref_req 以避免tREFI违规时，必须考虑每个待定请求的计时参数。为了考虑最坏的情况，减去每个bank machine的tRCD、CL、数据传输时间和tRP，以确保所有交易都能在tREFI到期之前完成。Equation 1-1显示了REF请求间隔的最大值。

Equation 1-1

A user REF should be issued immediately following calibration to establish a time baseline for determining when to send subsequent requests.

校准后应立即发布user REF，以确定何时发送后续请求的时间基线。

User ZQ

For user-controlled ZQ calibration, the Memory Controller managed maintenance should be disabled by setting the tZQI parameter to 0.

To request a ZQ command, app_zq_req is strobed for one cycle. When the Memory Controller sends the command to the PHY, it strobes app_zq_ack for one cycle, after which another request can be sent. Figure 1-84 illustrates the interface.

用户ZQ

对于用户控制的ZQ校准，应通过将tZQI参数设置为0来禁用内存控制器管理的维护。

为了请求ZQ命令，将app_zq_req选通一个周期。当内存控制器向物理层发送命令时，它将选通app_zq_ack一个周期，然后可以发送另一个请求。图1-84说明了界面。

A user ZQ operation can be performed any time provided the handshake defined above is followed. There are no additional interfacing requirements with respect to other commands.

However, pending requests affect when the operation goes out. The Memory Controller fulfills all pending data requests before issuing the ZQ command. Timing parameters must be considered for each pending request when determining when to strobe app_zq_req to achieve the desired interval if precision timing is desired.

遵循上面定义的握手出现，就可以随时执行用户ZQ操作。对于其他命令，没有额外的接口要求。但是，挂起的请求会影响操作何时停止。但是，挂起的请求会影响操作何时停止。内存控制器在发出ZQ命令之前完成所有挂起的数据请求。如果需要精确计时，则在确定何时选通app_zq_req以实现所需间隔时，必须考虑每个待定请求的计时参数。

To account for the worst case, subtract tRCD, CL, the data transit time and tRP for each bank machine to ensure that all transactions can complete before the target tZQI expires.

Equation 1-2 shows the ZQ request interval maximum.

A user ZQ should be issued immediately following calibration to establish a time baseline for determining when to send subsequent requests.