赛灵思的DDR IP手册ug586翻译和学习（5）第五章 Clocking使用方式

赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继

续上一篇，翻译和学习的是clocking，也就是时钟的相关知识。

Clocking（章节标题）

The 7 series FPGA MIG DDR3/DDR2 design has two clock inputs, the reference clock and the system clock. The reference clock drives the IODELAYCTRL components in the design, while the system clock input is used to create all MIG design clocks that are used to clock the internal logic, the frequency reference clocks to the phasers, and a synchronization pulse required for keeping PHY control blocks synchronized in multi-I/O bank implementations.For more information on clocking architecture, see Clocking Architecture, page 120.

7系列FPGA MIG DDR3/DDR2设计有两个时钟输入，参考时钟和系统时钟。参考时钟驱动设计中的IODELAYCTRL组件，而系统时钟输入用于创建所有MIG设计时钟，用于对内部逻辑、频率参考时钟到相位器进行时钟，以及在多输入/输出组实现中保持PHY控制块同步所需的同步脉冲。有关时钟体系结构的更多信息，请参阅时钟体系结构，第120页。

(P120的内容Clocking Architecture

The PHY design requires that a PLL module be used to generate various clocks, and both global and local clock networks are used to distribute the clock throughout the design. The PHY also requires one MMCM in the same bank as the PLL. This MMCM compensates for the insertion delay of the BUFG to the PHY.

The clock generation and distribution circuitry and networks drive blocks within the PHY that can be divided roughly into four separate, general functions:

• Internal (FPGA) logic

• Write path (output) I/O logic

• Read path (input) and delay I/O logic

• IDELAY reference clock

For DDR3 designs, one MMCM is required for IDELAY reference clock generation. If the design frequency is > 667 MHz, then IDELAY reference clock is either 300 MHz or 400 MHz (depending on FPGA speed grade). MIG instantiates one MMCM for 300 MHz and 400 MHz clock generation.)

物理层设计要求PLL模块用于生成各种时钟，全局和局部时钟网络用于在整个设计中分配时钟。物理层还需要与锁相环在同一组中有一个MMCM。该MMCM补偿BUFG到PHY的插入延迟。

物理层内的时钟生成和分配电路及网络驱动块大致可分为四个独立的通用功能：

•内部（FPGA）逻辑

•写入路径（输出）输入/输出逻辑

•读取路径（输入）和延迟输入/输出逻辑

•IDELAY参考时钟

对于DDR3设计，需要一个MMCM来生成IDELAY参考时钟。如果设计频率>667 MHz，则IDELAY参考时钟为300 MHz或400 MHz（取决于FPGA速度等级）。MIG实例化一个MMCM用于300 MHz和400 MHz时钟生成。）

The MIG tool allows you to input the Memory Clock Period and then lists available Input Clock Periods that follow the supported clocking guidelines. Based on these two clock periods selections, the generated MIG core appropriately sets the PLL parameters. The MIG tool enables automatic generation of all supported clocking structures. For information on how to use the MIG tool to set up the desired clocking structure including input clock placement, input clock frequency, and IDELAYCTRL ref_clk generation, see Creating 7Series FPGA DDR3 Memory Controller Block Design, page 32.

MIG工具允许您输入内存时钟周期，然后列出遵循支持的时钟准则的可用输入时钟周期。基于这两个时钟周期选择，生成的MIG磁芯适当设置PLL参数。MIG工具能够自动生成所有受支持的时钟结构。有关如何使用MIG工具设置所需时钟结构的信息，包括输入时钟位置、输入时钟频率和IDELAYCTRL refu clk生成，请参阅创建7系列FPGA DDR3内存控制器块设计，第32页。

Input Clock Guidelines

IMPORTANT: The input system clock cannot be generated internally.

• PLL Guidelines

° CLKFBOUT_MULT_F (M) must be between 1 and 16 inclusive.

° DIVCLK_DIVIDE (D, Input Divider) can be any value supported by the PLLE2 parameter.

° CLKOUT_DIVIDE (O, Output Divider) must be 2 for 400 MHz and up operation and 4 for below 400 MHz operation.

° The above settings must ensure the minimum PLL VCO frequency (FVCOMIN) is met. For specifications, see the appropriate DC and Switching Characteristics Data Sheet. The 7 Series FPGAs Clocking Resources User Guide (UG472) [Ref 10] includes the equation for calculating FVCO.

° The relationship between the input period and the memory period is InputPeriod = (MemoryPeriod × M)/(D × D1).

输入时钟准则

重要提示：无法在内部生成输入系统时钟。

•PLL指南

°CLKFBOUT_MULT_F (M)必须介于1和16之间（包括1和16）。

°DIVCLK_DIVIDE（D，输入除法器）可以是PLLE2支持的任何值参数

°CLKOUT_DIVIDE（O，输出分频器）对于400 MHz及以上操作必须为2，对于400 MHz以下操作必须为4。

°上述设置必须确保满足最小PLL压控振荡器频率（FVCOMIN）。有关规格，请参阅相应的直流和开关特性数据手册7系列FPGA时钟资源用户指南（UG472）[参考10]包括计算FVCO的等式。

°输入周期和存储周期之间的关系为InputPeriod=（MemoryPeriod×M）/（D×D1）。

The clock input (sys_clk) can be input on any CCIO in the column where the memory interface is located; this includes CCIO in banks that do not contain the memory interface, but must be in the same column as the memory interface. The PLL must be located in the bank containing the clock sent to the memory. To route the input clock to the memory interface PLL, the CMT backbone must be used. With the MIG implementation, one spare interconnect on the backbone is available that can be used for this purpose.

时钟输入（sys_clk）可以输入到内存接口所在列的任何CCIO上；这包括不包含内存接口但必须与内存接口位于同一列的存储组中的CCIO。PLL必须位于包含发送到内存的时钟的组中。为了将输入时钟路由到内存接口PLL，必须使用CMT主干。在MIG实施中，主干上有一个备用互连可用于此目的。

° MIG core versions 1.4 and later allow this input clocking setup and properly drive the CMT backbone.

° CLOCK_DEDICATED_ROUTE = BACKBONE constraint is used to implement CMT backbone, following warning message is expected. It can be ignored safely.

WARNING: [Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. The flow will continue as the CLOCK_DEDICATED_ROUTE constraint is set to BACKBONE.

u_mig_7series_0/c0_u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X0Y176

u_mig_7series_0/c0_u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X0Y1

u_mig_7series_0/c1_u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X0Y5

……

°MIG core版本1.4及更高版本允许此输入时钟设置，并正确驱动CMT主干。

°CLOCK_DEDICATED_ROUTE = BACKBONE约束用于实现CMT主干，预期会出现以下警告消息。可以安全地忽略它。

警告：[Place 30-172]具有时钟功能的IO引脚和PLL对的次优位置。当时钟专用路由约束设置为主干时，流将继续。

u_mig_7series_0/c0_u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O)锁定到IOB_X0Y176

u_mig_7series_0/c0_u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1)锁定到PLLE2_ADV_X0Y1

u_mig_7series_0/c1_u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1)锁定到PLLE2_ADV_X0Y5

……

• For DDR3 interfaces that have the memory system input clock (sys_clk) placed on CCIO pins within one of the memory banks, the MIG tool assigns the DIFF_SSTL15 I/O standard (VCCO = 1.5V) to the CCIO pins. Because the same differential input receiver is used for both DIFF_SSTL15 and LVDS inputs, an LVDS clock source can be connected directly to the DIFF_SSTL15 CCIO pins.

对于内存系统输入时钟（sys_clk）位于其中一个bank内CCIO引脚上的DDR3接口，MIG工具将DIFF_SSTL15输入/输出标准（VCCO=1.5V）分配给CCIO引脚。由于DIFF_SSTL15和LVDS输入使用相同的差分输入接收器，LVDS时钟源可以直接连接到DIFF_SSTL15 CCIO引脚。

• It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs). However, these criteria must be met:

a. The optional internal differential termination is not used (DIFF_TERM = FALSE, which is the default value).

Note: This might require manually changing DIFF_TERM parameter located in the top-level module or setting this in the UCF or XDC.

b. The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet.

c. The differential signals at the input pins meet the VIDIFF (min) requirements in the corresponding LVDS or LVDS_25 DC specifications tables of the specific device family data sheet.

输入/输出组中的LVDS和LVDS_25等差分输入是可以接受的，其供电电压水平不同于这些标准输出所需的标称电压（LVDS输出为1.8V，LVDS_25输出为2.5V）。但是，必须满足以下标准：

a、 不使用可选的内部差分终止（DIFF_TERM=FALSE，这是默认值）。

注意：这可能需要手动更改顶级模块中的DIFF_TERM参数，或在UCF或XDC中进行设置。

b、 输入引脚处的差分信号满足特定设备系列数据表中推荐操作条件表中的VIN要求。

c、 输入引脚处的差分信号满足特定设备系列数据表中相应LVDS或LVDS_25 DC规格表中的VIDIFF（最小值）要求。

One way to accomplish the above criteria is to use an external circuit that both AC-couples and DC-biases the input signals. The figure shows an example circuit for providing an AC-coupled and DC-biased circuit for a differential clock input. RDIFF provides the 100Ω differential receiver termination because the internal DIFF_TERM is set to FALSE. To maximize the input noise margin, all RBIAS resistors should be the same value, essentially creating a VICM level of VCCO/2. Resistors in the 10k to 100 kΩ range are recommended. The typical values for the AC coupling capacitors CAC are in the range of 100 nF. All components should be placed physically close to the FPGA inputs.

实现上述标准的一种方法是使用交流耦合和直流偏置输入信号的外部电路。该图显示了为差分时钟输入提供交流耦合和直流偏置电路的示例电路。RDIFF提供100Ω差分接收器端接，因为内部DIFF_项设置为FALSE。为了最大限度地提高输入噪声容限，所有RBIAS电阻器应具有相同的值，基本上产生了VCCO/2的VICM电平。建议使用10k至100kΩ范围内的电阻器。交流耦合电容器CAC的典型值在100 nF的范围内。所有组件应物理上靠近FPGA输入。

Figure 1-95: 交流耦合和直流偏置差分时钟输入示例电路

Note: The last set of guidelines on differential LVDS inputs are added within the LVDS and LVDS_25

(Low Voltage Differential Signaling) section of the 7 Series SelectIO Resources User Guide (UG471)

[Ref 2] in the next release of the document.

These guidelines are irrespective of Package, Column (HR/HP), or I/O Voltage.

注：LVDS和LVDS_25中添加了关于差分LVDS输入的最后一组指南7系列SelectIO资源用户指南（UG471）的（低压差分信号）部分[参考2]在下一版本的文件中。

这些指南与封装、列（HR/HP）或输入/输出电压无关。

Sharing sys_clk between Controllers（小标题）

在控制器之间共享系统时钟

The MIG 7 series FPGA designs require sys_clk to be in the same I/O bank column as the memory interface to minimize jitter.

• Interfaces Spanning I/O Columns – A single sys_clk input cannot drive memory interfaces spanning multiple I/O columns. The input clock input must be in the same column as the memory interface to drive the PLL using the CMT Backbone, which minimizes jitter.

• Interfaces in Single I/O Column – If the memory interfaces are entirely contained within the same I/O column, a common sys_clk can be shared among the interfaces.

The sys_clk can be input on any CCIO in the column where the memory interfaces are located. This includes CCIO in banks that do not contain the memory interfaces, but must be in the same column as the memory interfaces.

MIG 7系列FPGA设计要求sys_clk与内存接口位于同一输入/输出列中，以最小化抖动。

•跨输入/输出列的接口–单个sys_clk输入无法驱动跨多个输入/输出列的内存接口。输入时钟输入必须与内存接口位于同一列，以使用CMT主干驱动PLL，从而最大限度地减少抖动。

•单个输入/输出列中的接口–如果内存接口完全包含在同一输入/输出列中，则可以在接口之间共享一个公共系统时钟。

Sys_clk可以输入到内存接口所在列的任何CCIO上。这包括不包含内存接口但必须与内存接口位于同一列的存储组中的CCIO。

Information on Sharing BUFG Clock (phy_clk) （小标题）

关于共享BUFG时钟（phy_clk）的信息

The MIG 7 series DDR3 design includes an MMCM which outputs the phy_clk on a BUFG route. It is not possible to share this clock amongst multiple controllers to synchronize the user interfaces. This is not allowed because the timing from the FPGA logic to the PHY Control block must be controlled. This is not possible when the clock is shared amongst multiple controllers. The only option for synchronizing user interfaces amongst multiple controllers is to create an asynchronous FIFO for clock domain transfer.

MIG 7系列DDR3设计包括一个MMCM，该MMCM在BUFG路由上输出phy_clk。不可能在多个控制器之间共享该时钟以同步用户界面。这是不允许的，因为必须控制从FPGA逻辑到PHY控制块的定时。当时钟在多个控制器之间共享时，这是不可能的。在多个控制器之间同步用户界面的唯一选择是为时钟域传输创建异步FIFO。

Information on Sync_Pulse （小标题）

有关同步脉冲的信息

The MIG 7 series DDR3/DDR2 design includes one PLL that generates the necessary design clocks. One of these outputs is the sync_pulse. The sync pulse clock is 1/16 of the mem_refclk frequency and must have a duty cycle distortion of 1/16 or 6.25%. This clock is distributed across the low skew clock backbone and keeps all PHASER_IN/_OUT and PHY_Control blocks in sync with each other. The signal is sampled by the mem_refclk in both the PHASER_INs/_OUTs and PHY_Control blocks. The phase, frequency, and duty cycle of the sync_pulse is chosen to provide the greatest setup and hold margin across PVT.

MIG 7系列DDR3/DDR2设计包括一个PLL，用于生成必要的设计时钟。其中一个输出是sync_pulse。同步脉冲时钟为mem_refclk频率的1/16，占空比失真必须为1/16或6.25%。该时钟分布在低倾斜时钟主干上，并使所有相量输入/输出和物理单元控制块彼此同步。该信号由mem_refclk在相量输入/输出和物理控制块中进行采样。选择sync_pulse的相位、频率和占空比，以在PVT上提供最大的设置和保持裕度。