赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继
续上一篇，翻译和学习的是DDR3 SDRAM设计的design guidelines，也就是DDR3 SDRAM设计的指导原则。
P192
DDR3 SDRAM
This section describes guidelines for DDR3 SDRAM designs, including bank selection, pin allocation, pin assignments, termination, I/O standards, and trace lengths.
本节介绍DDR3 SDRAM设计的指导原则，包括存储体选择、引脚分配、引脚指定、端接、I/O标准和迹线长度。
Design Rules
Memory types, memory parts, and data widths are restricted based on the selected FPGA, FPGA speed grade, and the design frequency. The final frequency ranges are subject to characterization results.
内存类型、内存部件和数据宽度根据所选FPGA、FPGA速度等级和设计频率进行限制。最终频率范围取决于表征结果。
Bank and Pin Selection Guides for DDR3 Designs(小标题)
The MIG tool generates pin assignments for a memory interface based on physical layer rules.
MIG工具根据物理层规则为存储器接口生成引脚分配。
Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and certain rules must be followed to use the DDR3 SDRAM physical layer. Xilinx 7 series FPGAs have dedicated logic for each DQS byte group. Four DQS byte groups are available in each 50-pin bank. Each byte group consists of a clock-capable I/O pair for the DQS and 10 associated I/Os.
Xilinx 7系列FPGA专为高性能内存接口而设计，使用DDR3 SDRAM物理层必须遵循某些规则。Xilinx 7系列FPGA具有用于每个DQS字节组的专用逻辑。每个50引脚组中有四个DQS字节组。每个字节组包括用于DQ和10个相关I/O的具有时钟功能的I/O对。
Several times in this document byte groups are referenced for address and control as well, this refers to the 12 associated groups. In a typical DDR3 data bus configuration, eight of these 10 I/Os are used for the DQs, one is used for the data mask (DM), and one is left over for other signals in the memory interface.
在本文档中，地址和控制也多次引用字节组，这是指12个相关组。在典型的DDR3数据总线配置中，这10个I/O中有8个用于DQ，一个用于数据掩码（DM），另一个用于内存接口中的其他信号。
The MIG tool should be used to generate a pinout for a 7 series DDR3 interface. The MIG tool follows these rules:
• The system clock input must be in the same column as the memory interface. The system clock input is recommended to be in the address/control bank, when possible.
RECOMMENDED: Although the MIG allows system clock selection to be in different super logic regions
(SLRs), it is not recommended due to the additional clock jitter in this topology.
• CK must be connected to a p-n pair in one of the control byte groups. Any p-n pair in the group is acceptable, including SRCC, MRCC, and DQS pins.
• If multiple CK outputs are used, such as for dual rank, all CK outputs must come from the same byte lane.
• DQS signals for a byte group must be connected to a designated DQS pair in the bank due to the dedicated strobe connections for DDR2 and DDR3 SDRAM. For more information, see 7 Series FPGAs Clocking Resources User Guide (UG472) [Ref 10].
• DQ and DM (if used) signals must be connected to the byte group pins associated with the corresponding DQS.
• VRN and VRP are used for the digitally controlled impedance (DCI) reference for banks that support DCI.
• The non-byte groups pins (that is, VRN/VRP pins in HP banks and top/bottom most pins in HR banks) can be used for an address/control pin, if the following conditions are met:
° For HP banks, DCI cascade is used or the bank does not need the VRN/VRP pins, as in the case of only outputs.
° The adjacent byte group (T0/T3) is used as an address/control byte group.
° An unused pin exists in the adjacent byte group (T0/T3) or the CK output is contained in the adjacent byte group.
• No more than three vertical banks from a die perspective can be used for a single interface.
• The address/control must be in the middle I/O bank of interfaces that span three I/O banks. All address/control must be in the same I/O bank. Address/control cannot be split between banks.
• Control (RAS_N, CAS_N, WE_N, CS_N, CKE, ODT) and address lines must be connected to byte groups not used for the data byte groups.
• RESET_N can be connected to any available pin within the device, including the VRN/VRP pins if DCI cascade is used, as long as timing is met and an appropriate I/O voltage standard is used. The GUI restricts this pin to the banks used for the interface to help with timing, but this is not a requirement.
• Devices implemented with SSI technology have SLRs. Memory interfaces cannot span across SLRs. Ensure that this rule is followed for the part chosen and for any other pin-compatible parts that can also be used.
MIG工具应用于为7系列DDR3接口生成引脚。MIG工具遵循以下规则：
•系统时钟输入必须与内存接口位于同一列。如果可能，建议将系统时钟输入置于地址/控制库中。
推荐：尽管MIG允许系统时钟选择在不同的超级逻辑区域
由于这种拓扑结构中存在额外的时钟抖动，因此不建议使用。
•CK必须连接到其中一个控制字节组中的p-n对。组中的任何p-n对均可接受，包括SRCC、MRCC和DQS引脚。
•如果使用多个CK输出，例如双rank，则所有CK输出必须来自同一字节通道。
•由于DDR2和DDR3 SDRAM的专用选通连接，字节组的DQS信号必须连接到存储体中的指定DQS对。有关更多信息，请参阅7系列FPGA时钟资源用户指南（UG472）[参考文献10]。
•DQ和DM（如果使用）信号必须连接到与相应DQ相关的字节组引脚。
•VRN和VRP用于支持DCI的bank的数字控制阻抗（DCI）参考。
•如果满足以下条件，则非字节组引脚（即HP组中的VRN/VRP引脚和HR组中的最顶部/最底部引脚）可用于地址/控制引脚：
•地址/控制必须位于跨越三个输入/输出组的接口的中间输入/输出库中。所有地址/控制必须在同一个I/O存储体中。地址/控件不能在银行之间拆分。
•控制（RAS_ N、CAS_N、WE_N和CS_N，CKE、ODT）和地址线必须连接到不用于数据字节组的字节组。
•RESET_。GUI将此pin限制为用于接口的存储体，以帮助计时，但这不是一项要求。
•采用SSI技术的设备具有单反相机。内存接口不能跨越SLR。确保所选零件和任何其他也可使用的引脚兼容零件遵循此规则。
Pin Swapping(大标题)引脚交换
• Pins can be freely swapped within each byte group (data and address/control), except for the DQS pair which must be on a clock-capable DQS pair and the CK which must be on a p-n pair.
• Byte groups (data and address/control) can be freely swapped with each other.
• Pins in the address/control byte groups can be freely swapped within and between their byte groups.
• No other pin swapping is permitted.
•引脚可以在每个字节组（数据和地址/控制）内自由交换，但DQS对必须在具有时钟功能的DQS对中，CK必须在p-n对中。
•字节组（数据和地址/控制）可以彼此自由交换。
•地址/控制字节组中的引脚可在其字节组内和之间自由交换。
•不允许进行其他引脚交换。
