赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继
续上一篇，翻译和学习的是DDR3 SDRAM设计的Bank Sharing Among Controllers等电路方面的设计准则。
Bank Sharing Among Controllers（小标题）
No unused part of a bank used in a memory interface is permitted to be shared with another memory interface. The dedicated logic that controls all the FIFOs and phasers in a bank is designed to only operate with a single memory interface and cannot be shared with other memory interfaces. With the exception of the shared address and control in the dual controller supported in the MIG core.
控制者之间的bank共享(小标题）
存储器接口中使用的存储体的未使用部分不允许与另一个存储器接口共享。控制存储体中所有FIFO和相位器的专用逻辑设计为仅使用单个内存接口操作，不能与其他内存接口共享。除了MIG核心中支持的双控制器中的共享地址和控制之外。
System Clock, PLL and MMCM Locations, and Constraints（小标题）
The PLL and MMCM are required to be in the bank that supplies the clock to the memory to meet the specified interface performance. The system clock input is also strongly recommended to be in this bank. The MIG tool follows these two rules whenever possible. The exception is a 16-bit interface in a single bank where there might not be pins available for the clock input. In this case, the clock input needs to come from an adjacent bank through the frequency backbone to the PLL. The system clock input to the PLL must come from clock capable I/O.
系统时钟、PLL和MMCM位置以及约束(小标题）
PLL和MMCM需要位于向存储器提供时钟的存储体中，以满足指定的接口性能。强烈建议将系统时钟输入置于该库中。MIG工具尽可能遵循这两条规则。例外情况是单个存储体中的16位接口，其中可能没有可用于时钟输入的引脚。在这种情况下，时钟输入需要来自相邻的组，通过频率主干到达PLL。PLL的系统时钟输入必须来自具有时钟功能的I/O。
The system clock input can only be used for an interface in the same column. If the clock came from another column, the additional PLL or MMCM and clock routing required for this induces too much additional jitter.
Unused outputs from the PLL can be used as clock outputs. Only the settings for these outputs can be changed. Settings related to the overall PLL behavior and the used outputs must not be disturbed.
A PLL cannot be shared among interfaces. See Clocking Architecture, page 120 for information on allowed PLL parameters.
系统时钟输入只能用于同一列中的接口。如果时钟来自另一列，则额外的PLL或MMCM以及为此所需的时钟路由会导致太多额外的抖动。
来自PLL的未使用输出可用作时钟输出。只能更改这些输出的设置。不得干扰与整个PLL行为和所用输出相关的设置。
PLL不能在接口之间共享。有关允许的PLL参数的信息，请参见第120页的时钟体系结构。
DDR3 Component PCB Routing（小标题）
Fly-by routing topology is required for the clock, address, and control lines. Fly-by means that this group of lines is routed in a daisy-chain fashion and terminated appropriately at the end of the line. The trace length of each signal within this group to a given component must be matched. The controller uses write leveling to account for the different skews between components. This technique uses fewer FPGA pins because signals do not have to be replicated. The data bus routing for each component should be as short as possible. Each signal should be routed on a single PCB layer to minimize discontinuities caused by additional vias.
DDR3组件PCB布线(小标题）
时钟、地址和控制线需要飞接路由拓扑。飞越是指这组线路以菊花链方式布线，并在线路末端适当终止。该组中每个信号到给定分量的轨迹长度必须匹配。控制器使用写平衡来考虑组件之间的不同倾斜。这种技术使用较少的FPGA引脚，因为信号不必复制。每个组件的数据总线路由应尽可能短。每个信号应在单个PCB层上布线，以最小化额外通孔造成的不连续性。
VREF（小标题）
The VREF includes internal and external:
• Internal VREF – Only be used for data rates of 800 Mb/s or below.
• External VREF and VREF Tracking – For the maximum specified data rate in a given FPGA speed grade, external VREF must track the midpoint of the VDD supplied to the DRAM and ground. VREF tracking can be done with a resistive divider or by a regulator that tracks this midpoint. Regulators that supply a fixed reference voltage irrespective of the VDD voltage should not be used at these data rates. VREF traces need to have a larger than the minimum spacing to reduce coupling from other intrusive signals. See 7 Series FPGAs PCB Design and Pin Planning Guide (UG483) [Ref 12], “VREF Stabilization Capacitors” section.
VREF(小标题）
VREF包括内部和外部：
•内部VREF–仅用于800 Mb/s或以下的数据速率。
•外部VREF和VREF跟踪–对于给定FPGA速度等级中的最大指定数据速率，外部VREF必须跟踪提供给DRAM和地面的VDD的中点。VREF跟踪可通过电阻分频器或跟踪该中点的调节器完成。在这些数据速率下，不应使用提供固定参考电压而不考虑VDD电压的稳压器。VREF迹线需要具有大于最小间距的间距，以减少来自其他侵入信号的耦合。参见7系列FPGA PCB设计和引脚规划指南（UG483）[参考12]，“VREF稳定电容器”部分。
VCCAUX_IO（小标题）
VCCAUX_IO has two values that can be set to 1.8V or 2.0V depending on memory performance. If migration occurs between different memory performance or FPGA speed grades, VCCAUX_IO might need to be its own supply that can be adjusted. For performance information, see the 7 Series FPGAs Data Sheets [Ref 13]
For more information on VCCAUX_IO, see 7 Series SelectIO™ Resources User Guide (UG471) [Ref 2], “VCCAUX_IO” section.
VCCAUX_ IO(小标题）
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