赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继续上一篇，翻译和学习的是DDR3的约束和配置。
Configuration(小标题) 配置
The XDC contains timing, pin, and I/O standard information. The sys_clk constraint sets the operating frequency of the interface and is set through the MIG GUI. This must be rerun if this needs to be altered, because other internal parameters are affected.
XDC包含定时、引脚和I/O标准信息。sys_clk约束设置接口的工作频率，并通过MIG GUI进行设置。如果需要更改，则必须重新运行，因为其他内部参数会受到影响。例如：
For example:
create_clock -period 1.875 [get_ports sys_clk_p]
The clk_ref constraint sets the frequency for the IDELAY reference clock, which is typically 200 MHz.
clk_ ref约束设置IDELAY参考时钟的频率，通常为200 MHz。例如：
For example:
create_clock -period 5 [get_ports clk_ref_p]
The I/O standards are set appropriately for the DDR3 interface with LVCMOS15, SSTL15, SSTL15_T_DCI, DIFF_SSTL15, or DIFF_SSTL15_T_DCI, as appropriate. LVDS_25 is used for the system clock (sys_clk) and I/O delay reference clock (clk_ref). These standards can be changed, as required, for the system configuration. These signals are brought out to the top-level for system connection:
DDR3接口的电平标准可以为LVCMOS15, SSTL15, SSTL15_T_ DCI、DIFF_SSTL15或DIFF_ SSTL15_ T_DCI。LVDS_ 25用于系统时钟（sys_clk）和I/O延迟参考时钟（clk_ref）。这些标准可以根据需要为系统配置进行更改。这些信号被带到顶层用于系统连接：
• sys_rst – This is the main system reset (asynchronous). The reset signal must be applied for a minimum pulse width of 5 ns. 这是主系统复位（异步）。复位信号的最小脉冲宽度必须为5ns。
• init_calib_complete – This signal indicates when the internal calibration is done and that the interface is ready for use. 该信号指示何时完成内部校准，并且接口已准备好使用。
• tg_compare_error – This signal is generated by the example design traffic generator if read data does not match the write data. 如果读取数据与写入数据不匹配，则该信号由示例设计流量生成器生成。
These signals are all set to LVCMOS25 and can be altered as needed for the system design. They can be generated and used internally instead of being brought out to pins.
这些信号均设置为LVCMOS25，并可根据系统设计需要进行更改。它们可以在内部生成和使用，而不是输出到引脚。
A 16-bit wide interfaces might need to have the system clock in a bank above or below the bank with the address/control and data. In this case, the MIG tool puts an additional constraint in the XDC. An example is shown here:
16位宽的接口可能需要在具有地址/控制和数据的存储体之上或之下的存储器中具有系统时钟。在这种情况下，MIG刀具在XDC中施加了额外的约束。此处显示了一个示例：
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_p]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hierarchical *pll*CLKIN1]
This results in a warning listed below during PAR. This warning can be ignored.
这将导致在PAR期间出现以下警告。可以忽略此警告。
WARNING:Place:1402 – A clock IOB / PLL clock component pair have been found that are not placed at an optimal clock IOB / PLL site pair. The clock IOB component <sys_clk_p> is placed at site <IOB_X1Y76>. The corresponding PLL component <u_backb16/u_ddr3_infrastructure/plle2_i> is placed at site <PLLE2_ADV_X1Y2>. The clock I/O can use the fast path between the IOB and the PLL if the IOB is placed on a Clock Capable IOB site that has dedicated fast path to PLL sites within the same clock region. You might want to analyze why this issue exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <sys_clk_p.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it might lead to very poor timing results. It is recommended that this error condition be corrected in the design.
Do not drive user clocks through the I/O clocking backbone from the region(s) containing the MIG generated memory interface to CMT blocks in adjacent regions due to resource limitations. For more information, see the 7 Series FPGAs Clocking Resources User Guide (UG472) [Ref 10].
The MIG tool sets the VCCAUX_IO constraint based on the data rate and voltage input selected. The generated XDC has additional constraints as needed. For example:
由于资源限制，请勿通过I/O时钟主干将用户时钟从包含MIG生成存储器接口的区域驱动到相邻区域中的CMT块。有关更多信息，请参阅7系列FPGA时钟资源用户指南（UG472）[参考文献10]。
MIG工具根据选择的数据速率和电压输入设置VCCAUX_ IO约束。生成的XDC根据需要具有附加约束。例如：
Consult the Constraints Guide for more information.
For DDR3 SDRAM interfaces that have the memory system input clock (sys_clk_p/sys_clk_n) placed on CCIO pins within one of the memory banks, the MIG tool assigns the DIFF_SSTL15 I/O standard (VCCO = 1.5V) to the CCIO pins. Because the same differential input receiver is used for both DIFF_SSTL15 and LVDS inputs, an LVDS clock source can be connected directly to the DIFF_SSTL15 CCIO pins. For more details on usage and required circuitry for LVDS and LVDS_25 I/O Standards, see the 7 Series FPGAs SelectIO™ Resources User Guide (UG471) [Ref 2].
有关更多信息，请参阅《约束指南》。
对于内存系统输入时钟（sys_clk_p/sys_ clk_ n）位于其中一个内存库内CCIO引脚上的DDR3 SDRAM接口，MIG工具将DIFF_SSTL15 I/O标准（VCCO=1.5V）分配给CCIO引脚。由于相同的差分输入接收器用于DIFF_ SSTL15和LVDS输入，因此LVDS时钟源可以直接连接到DIFF_ SSTL15。有关LVDS和LVDS_25 I/O标准的使用和所需电路的更多详细信息，请参阅7系列FPGA SelectIO™ 参考资料用户指南（UG471）[参考文献2]。
I/O Standards(小标题) I/O标准
These rules apply to the I/O standard selection for DDR3 SDRAMs:
这些规则适用于DDR3 SDRAM的I/O标准选择：
• Designs generated by the MIG tool use the SSTL15_T_DCI and DIFF_SSTL15_T_DCI standards for all bidirectional I/O (DQ, DQS) in the High-Performance banks. In the High-Range banks, the tool uses the SSTL15 and DIFF_SSTL15 standard with the internal termination (IN_TERM) attribute chosen in the GUI. 在高性能bank中，该MIG工具的双向IO（DQ, DQS）使用SSTL15_T_DCI和DIFF_SSTL15_T_DCI标准，在high range bank中，用SSTL15 and DIFF_SSTL15电平标准的工具在GUI中选择内部终止（IN_TERM）属性。
• The SSTL15 and DIFF_SSTL15 standards are used for unidirectional outputs, such as control/address, and forward memory clocks. SSTL15和DIFF_ SSTL15标准用于单向输出，如控制/地址和正向存储器时钟。
• LVCMOS15 is used for the RESET_N signal driven to the DDR3 memory. LVCMOS15用于驱动到DDR3存储器的RESET_ N信号。
The MIG tool creates the XDC using the appropriate standard based on input from the GUI.
MIG工具根据GUI的输入，使用适当的标准创建XDC。
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