赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继
续上一篇，翻译和学习的是Debug Tools调试工具。
P230
Debug Signals(小标题) 调试信号
The MIG 7 series tool includes a Debug Signals Control option on the FPGA Options screen. Enabling this feature allows calibration, tap delay, and read data signals to be monitored using the Vivado logic analyzer feature. Selecting this option port maps the debug signals to ILA VIO cores in the design top module. For details on enabling this debug feature, see the “Using MIG in the Vivado Design Suite, page 21. The debug port is disabled for functional simulation and can only be enabled if the signals are actively driven by the user design.
MIG 7系列工具包括FPGA选项屏幕上的调试信号控制选项。启用此功能允许使用Vivado逻辑分析仪功能监控校准、抽头延迟和读取数据信号。选择此选项端口将调试信号映射到design top模块中的ILA VIO内核。有关启用此调试功能的详细信息，请参阅“在Vivado设计套件中使用MIG”，第21页。功能模拟禁用调试端口，只有在用户设计主动驱动信号时才能启用。
Note: “Debug Signals” are not available when using IP integrator but Integrated Logic Analyzer (ILA) insertion is still available on the synthesized DCP. For more information, see the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 16].
注：使用IP积分器时，“调试信号”不可用，但在合成DCP上仍然可以插入集成逻辑分析仪（ILA）。有关更多信息，请参阅Vivado Design Suite用户指南：编程和调试（UG908）[参考文献16]。
Vivado Design Suite Debug Feature(小标题) Vivado设计套件调试功能
The Vivado Design Suite debug feature inserts ILA 3.0 and VIO 3.0 directly into your design.The debug feature also allows you to set trigger conditions to capture application and MIG debug signals in hardware. Captured signals can be analyzed though the Vivado logic analyzer feature. For more information about the Vivado logic see the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 16].
Vivado设计套件调试功能将ILA 3.0和VIO 3.0直接插入到您的设计中。调试功能还允许您设置触发条件，以捕获硬件中的应用程序和MIG调试信号。捕获的信号可以通过Vivado逻辑分析仪功能进行分析。有关Vivado逻辑的更多信息，请参阅Vivado设计套件用户指南：编程和调试（UG908）[参考文献16]。
IMPORTANT: The ILA operates on a synchronous clock and cannot be triggered during reset. Instead, set the trigger on an ILA signal to look for a rising edge (“R”) or falling edge (“F”) with the radix value of the signal set to “Binary.” With this trigger setting, the trigger can be armed. When the reset is applied and released, the trigger captures the desired ILA results.
Reference Boards(小标题) 参考板
Various Xilinx development boards support MIG IP core that include FPGA interfaces to a DDR SODIMM. These boards can be used to prototype designs and establish that the core can communicate with the system.
• 7 series FPGA evaluation boards
° VC707
° KC705
° AC701
各种Xilinx开发板支持MIG IP核，包括与DDR SODIMM的FPGA接口。这些板可用于原型设计，并确定核心可与系统通信。
•7系列FPGA评估板
°VC707
°KC705
°AC701
Hardware Debug(小标题)
Hardware issues can range from calibration failures to issues seen after hours of testing. This section provides debug steps for common issues. The Vivado logic analyzer feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the Vivado logic analyzer feature for debugging the specific issues.
硬件调试(小标题)
硬件问题的范围从校准故障到数小时测试后出现的问题。本节提供常见问题的调试步骤。Vivado逻辑分析器功能是用于硬件调试的宝贵资源。可以使用Vivado逻辑分析器功能来探测以下各节中提到的信号名称，以调试特定问题。
Many of these common issues can also be applied to debugging design simulations. Details are provided on:
• General Checks
• Calibration Stages
• Determine the Failing Calibration Stage
• Debug Signals
• Debugging PHASER_IN PHASELOCKED Calibration Failures (dbg_pi_phaselock_err = 1)
• Debugging PHASER_IN DQSFOUND Calibration Failures (dbg_pi_dqsfound_err = 1)
• Debugging Write Leveling Failures (dbg_wrlvl_err = 1)
• Debugging MPR Read Leveling Failures – DDR3 Only (dbg_rdlvl_err[1] = 1)
• Debugging OCLKDELAYED Calibration Failures
• Debugging Write Calibration Failures (dbg_wrcal_err = 1)
• Debugging Read Leveling Failures (dbg_rdlvl_err[0] = 1)
• Debugging PRBS Read Leveling Failures
• Calibration Times
• Debugging Data Errors
这些常见问题中的许多也可以应用于调试设计模拟。详情如下：
•一般检查
•校准阶段
•确定故障校准阶段
•调试信号
•调试PHASER_IN锁相校准故障（dbg_pi_phaselock_err=1）
•调试PHASER_IN DQSFOUND校准故障（dbg_pi_DQSFOND_err=1）
•调试写平衡故障（dbg_wrlvl_err=1）
•调试MPR读调平故障–仅DDR3（dbg_rdlvl_err[1]=1）
•调试OCLK延迟校准故障
•调试写入校准失败（dbg_wrcal_err=1）
•调试读调平失败（dbg_rdlvl_err[0]=1）
•调试PRB读平衡故障
•校准时间
•调试数据错误
General Checks(小标题) 一般检查
This section details the list of general checks, primarily board level, which need to be verified before moving forward with the debug process. Strict adherence to the proper board design is critical in working with high speed memory interfaces.
• Ensure all guidelines referenced in the Design Guidelines have been followed. The Design Guidelines section includes information on trace matching, PCB Routing, noise, termination, I/O Standards, and pin/bank requirements. Adherence to these guidelines, along with proper board design and signal integrity analysis, is critical to the success of high-speed memory interfaces.
本节详细介绍了在继续调试过程之前需要验证的常规检查列表，主要是板级检查。严格遵守正确的电路板设计对于使用高速存储器接口至关重要。
•确保遵循设计指南中引用的所有指南。设计指南部分包括关于迹线匹配、PCB布线、噪声、终端、I/O标准和引脚/存储体要求的信息。遵守这些准则，以及正确的板设计和信号完整性分析，对于高速存储器接口的成功至关重要。
• Measure all voltages on the board during idle and non-idle times to ensure the voltages are set appropriately and noise is within specifications.
° Ensure the termination voltage regulator (Vtt) is turned on (set to 0.75V).
° Ensure VREF is measured.
• When applicable, check VRN/VRP resistors. Note the values are not the same as Virtex-6 FPGA.
• Look at the clock inputs to ensure they are clean.
• Check the reset to ensure the polarity is correct and the signal is clean. The reset signal must be applied for a minimum pulse width of 5 ns.
• Check terminations by using this user guide as a guideline.
• Perform general signal integrity analysis.
° IBIS simulations should run to ensure terminations, ODT, and output drive strength settings are appropriate.
° Observe DQ/DQS on a scope at the memory. View the alignment of the signals and analyze the signal integrity during both writes and reads.
° Observe the Address and Command signals on a scope at the memory. View the alignment and analyze the signal integrity.
•在空闲和非空闲时间测量电路板上的所有电压，以确保电压设置正确，噪声在规范范围内。
°确保终端电压调节器（Vtt）打开（设置为0.75V）。
°确保测量VREF。
•适用时，检查VRN/VRP电阻器。注意，这些值与Virtex-6 FPGA不同。
•查看时钟输入，确保其干净。
•检查复位，确保极性正确，信号干净。复位信号的最小脉冲宽度必须为5ns。
•使用本用户指南作为指南检查终端。
•执行一般信号完整性分析。
°应运行IBIS模拟，以确保终端、ODT和输出驱动强度设置适当。
°在存储器的示波器上观察DQ/DQS。查看信号对齐情况，并分析写入和读取期间的信号完整性。
°观察存储器示波器上的地址和命令信号。查看对准并分析信号完整性。
• Verify the memory parts on the board(s) in test are the correct part(s) set through the MIG tool. The timing parameters and signals widths (that is, address, bank address) must match between the RTL and physical parts. Read/write failures can occur due to a mismatch.
• Verify SDRAM pins are behaving correctly. Look for floating or grounded signals. It is rare, but manufacturing issues with the memory devices can occur and result in calibration failures.
• If Data Mask (DM) is not being used, ensure DM is tied Low at the memory with the appropriate termination as noted in the memory data sheet.
• Measure the CK/CK_n, DQS/DQS_n, and system clocks for duty cycle distortion and general signal integrity.
• If internal VREF is used, ensure the constraints are set appropriately according to the Xilinx Constraints Guide. When the constraints are applied properly, a note similar to the following appears in the .bgn BitGen report file:
° There were two CONFIG constraint(s) processed from example_top.pcf.
CONFIG INTERNAL_VREF_BANK12 = 0.75
CONFIG INTERNAL_VREF_BANK14 = 0.75
• Check the iodelay_ctrl ready signal.
• Check the PLL lock.
• Check the phaser_ref lock signal.
• Bring the init_calib_complete out to a pin and check with a scope.
•验证测试板上的存储部件是否为通过MIG工具设置的正确部件。时序参数和信号宽度（即地址、存储体地址）必须在RTL和物理部分之间匹配。由于不匹配，可能会发生读/写故障。
•验证SDRAM引脚是否正常工作。寻找浮动或接地信号。这很少见，但可能会出现内存设备的制造问题，并导致校准失败。
•如果未使用数据掩码（DM），请确保DM在内存中处于低位，并按照内存数据表中的说明使用适当的终端。
•测量CK/CK_ n、DQS/DQS_。
•如果使用内部VREF，确保根据Xilinx约束指南适当设置约束。当约束正确应用时，.bgn BitGen报告文件中会出现类似于以下内容的注释：
°从example_top.pcf处理了两个配置约束。
配置INTERNAL_VREF_BANK12=0.75
配置内部_VREF_BANK14=0.75
•检查iodelay_ctrl就绪信号。
•检查PLL锁。
•检查phaser_ref锁定信号。
•将init_calib_complete带到引脚，并使用示波器进行检查。
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