赛灵思的DDR IP手册ug586翻译和学习（10）第十章 DDR校准

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赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继

续上一篇，翻译和学习的是DDR校准。

Figure 1-97: Calibration Stages

1 System Reset

2 DDR2/DDR3 SDRAM Initialization

3 Phaser_IN Phase Lock (Phase Locks Read DQS to Internal, Free-Running Frequency Reference Clock)

4 Phaser_In DQSFOUND Calibration

5 Write Leveling (For DDR3 SDRAM Only)

6 Multi-Purpose Register (MPR) Read Leveling (Center Read DQS in Read DQ Window Independent of Writes)

7 OCLKDELAYED Calibration (Center Write DQS in Write DQ Window Using MMCM Phase Shift)

8 Write Calibration (Aligning Write DQS to the Correct CK/CK# Edge)

9 Read Leveling (Initial DQ Alignment to DQS and DQS Centering in Read DQ Window)

10 PRBS Read Leveling (Read DQS Centering in Read DQ Window with PRBS Pattern to Account for ISI Effects)

11 PHY Initialization and Calibration Complete

图1-97：校准阶段

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P234 Memory Initialization

The PHY executes a JEDEC-compliant DDR2 or DDR3 initialization sequence following the deassertion of system reset. Each DDR2 or DDR3 SDRAM has a series of mode registers accessed through Mode Register Set (MRS) commands. These mode registers determine various SDRAM behaviors, such as burst length, read and write CAS latency, and additive latency. The MIG 7 series designs does not issue a calibration failure during Memory Initialization.

All other initialization/calibration stages are reviewed in the following Debugging Calibration Stages section.

P234内存初始化

PHY在系统复位解除置1之后执行符合JEDEC的DDR2或DDR3初始化序列。每个DDR2或DDR3 SDRAM具有通过模式寄存器集（MRS）命令访问的一系列模式寄存器。这些模式寄存器决定各种SDRAM行为，如突发长度、读写CAS延迟和附加延迟。MIG 7系列设计在存储器初始化期间不会出现校准故障。

所有其他初始化/校准阶段将在以下调试校准阶段部分进行审查。

Determine the Failing Calibration Stage

Using the Vivado logic analyzer feature, configure the device along with debug_nets.ltxfile. This file can be found in the example.runsimpl_1 directory after implementation completes with Debug_port feature enabled. Observe the following debug signals in the provided ILA core. This indicates which calibration stage failed:

确定失败的校准阶段

使用Vivado逻辑分析器功能，将设备与debug_nets.ltxfile一起配置。该文件可以在示例中找到。在启用调试端口功能的实现完成后运行impl_1目录。在提供的ILA核心中观察以下调试信号。这表明哪个校准阶段失败：

Table 1-73: DDR2/DDR3 Basic ILA Debug Signals

Signal Name	Description
init_calib_complete	Signifies memory initialization and calibration have completed successfully. 表示内存初始化和校准已成功完成。
dbg_wrlvl_start	Signifies the start of the Write Leveling stage of calibration. 表示校准的写入均衡阶段的开始。
dbg_wrlvl_done	Signifies successful completion of the Write Leveling stage of calibration. 表示校准的写入均衡阶段成功完成。
dbg_wrlvl_err	Signifies the Write Leveling stage of calibration exhibited errors and did not complete. 表示校准的写入均衡阶段出现错误且未完成。
dbg_pi_phaselock_start	Signifies the start of the PHASELOCK stage of calibration. 表示校准相位锁定阶段的开始。
dbg_pi_phaselock_done	Signifies successful completion of the PHASELOCK stage of calibration. 表示校准的相位锁定阶段成功完成。
dbg_pi_phaselock_err	Signifies the PHASELOCK stage of calibration exhibited errors and did not complete. 表示校准的相位锁定阶段出现错误且未完成。
dbg_pi_dqsfound_start	Signifies the start of the DQSFOUND stage of calibration. 表示校准的DQSFOUND阶段开始。
dbg_pi_dqsfound_done	Signifies successful completion of the DQSFOUND stage of calibration. 表示校准的DQSFOUND阶段成功完成。
dbg_pi_dqsfound_err	Signifies the DQSFOUND stage of calibration exhibited errors and did not complete. 表示校准的DQSFOUND阶段出现错误且未完成。
dbg_rdlvl_start[0]	Signifies the start of Read Leveling Stage 1 calibration. 表示读取调平阶段1校准的开始。
dbg_rdlvl_start[1]	Signifies the start of the MPR stage of calibration. 表示MPR校准阶段的开始。
dbg_rdlvl_done[0]	Signifies the successful completion of Read Leveling Stage 1 calibration. 表示读取均衡阶段1校准成功完成。
dbg_rdlvl_done[1]	Signifies the successful completion of the MPR Stage of calibration. 表示校准的MPR阶段成功完成。
dbg_rdlvl_err[0]	Signifies Read Leveling Stage 1 calibration exhibited errors and did not complete. 表示读取均衡阶段1校准显示错误且未完成。
dbg_rdlvl_err[1]	Signifies the MPR stage of calibration exhibited errors and did not complete. 表示校准的MPR阶段出现错误且未完成。
dbg_oclkdelay_calib_start	Signifies the start of the OCLKDELAY stage of calibration. 表示校准的OCLK延迟阶段开始。
dbg_oclkdelay_calib_done	Signifies successful completion of the OCLKDELAY stage of calibration. 表示校准的OCLK延迟阶段成功完成。
dbg_wrcal_start	Signifies the start of the Write Calibration stage of calibration. 表示校准的写入校准阶段的开始。
dbg_wrcal_done	Signifies successful completion of the Write Calibration stage of calibration. 表示校准的写入校准阶段成功完成。
dbg_wrcal_err	Signifies Write Calibration exhibited errors and did not complete. 表示写入校准显示错误且未完成。

Debug Signals
Table 1-74: DDR2/DDR3 Debug Signals

Signal Name	Description
ILA Signals (Status)
dbg_init_calib_complete	Signifies memory initialization and calibration have completed successfully. 表示内存初始化和校准已成功完成。
dbg_wrlvl_start	Signifies the start of the Write Leveling stage of calibration. 表示校准的写入均衡阶段的开始。
dbg_wrlvl_done	Signifies successful completion of the Write Leveling stage of calibration. 表示校准的写入均衡阶段成功完成。
dbg_wrlvl_err	Signifies the Write Leveling stage of calibration exhibited errors and did not complete. 表示校准的写入均衡阶段出现错误且未完成。
dbg_pi_phaselock_start	Signifies the start of the PHASELOCK stage of calibration. 表示校准相位锁定阶段的开始。
dbg_pi_phaselocked_done	Signifies successful completion of the PHASELOCK stage of calibration. 表示校准的相位锁定阶段成功完成。
dbg_pi_phaselock_err	Signifies the PHASELOCK stage of calibration exhibited errors and did not complete. 表示校准的相位锁定阶段出现错误且未完成。
dbg_pi_dqsfound_start	Signifies the start of the DQSFOUND stage of calibration. 表示校准的DQSFOUND阶段开始。
dbg_pi_dqsfound_done	Signifies successful completion of the DQSFOUND stage of calibration. 表示校准的DQSFOUND阶段成功完成。
dbg_pi_dqsfound_err	Signifies the DQSFOUND stage of calibration exhibited errors and did not complete. 表示校准的DQSFOUND阶段出现错误且未完成。
dbg_rdlvl_start[1]	Signifies the start of the MPR stage of calibration. 表示MPR校准阶段的开始。
dbg_rdlvl_start[0]	Signifies the start of Read Leveling Stage 1 calibration. 表示读取均衡阶段1校准的开始。
dbg_rdlvl_done[1]	Signifies the successful completion of the MPR Stage of calibration. 表示校准的MPR阶段成功完成。
dbg_rdlvl_done[0]	Signifies the successful completion of Read Leveling Stage 1 calibration. 表示读取均衡阶段1校准成功完成。
dbg_rdlvl_err[1]	Signifies Read Leveling Stage 1 calibration exhibited errors and did not complete.表示读取均衡阶段1校准显示错误且未完成
dbg_rdlvl_err[0]	Signifies the MPR stage of calibration exhibited errors and did not complete. 表示校准的MPR阶段出现错误且未完成。
dbg_oclkdelay_calib_start	Signifies the start of the OCLKDELAY stage of calibration. 表示校准的OCLK延迟阶段开始。
dbg_oclkdelay_calib_done	Signifies successful completion of the OCLKDELAY stage of calibration. 表示校准的OCLK延迟阶段成功完成。
dbg_wrcal_start	Signifies the start of the Write Calibration stage of calibration. 表示校准的写入校准阶段的开始。
dbg_wrcal_done	Signifies successful completion of the write calibration stage of calibration. 表示校准的写入校准阶段成功完成。
dbg_wrcal_err	Signifies write calibration exhibited errors and did not complete. 表示写入校准显示错误且未完成。
dbg_phy_init_5_0	State variable for the PHY Init state machine. States can be decoded in the ddr_phy_init module. PHY Init状态机的状态变量。可以在ddr_phy_init模块中解码状态。
dbg_rddata_valid_r	Asserts when the read data (dbg_rddata_r) is valid. 当读取数据（dbg_rddata_r）有效时置1。

dbg_rddata_r	Read data read out of the IN_FIFO for the DQS group selected through dbg_dqs on the VIO. This is a 64-bit bus. This debug port does not capture ECC data. 读取通过VIO上的dbg_DQS选择的DQS组从IN_FIFO读出的数据。这是一条64位总线。此调试端口不捕获ECC数据。
dbg_fine_adjust_done_r	Asserts after fine adjustment is completed in DQS found calibration. 在DQS发现校准中完成微调后置1。
dbg_cmd_wdt_err_w	Watch dog timeout error from Traffic Generator when the user interface is not processing the command from traffic generator. 当用户界面未处理来自流量生成器的命令时，流量生成器出现看门狗超时错误。
dbg_rd_wdt_err_w	Watch dog timeout error from Traffic Generator when no read data is available from the user interface. 当用户界面没有可用的读取数据时，流量生成器出现看门狗超时错误。
dbg_wr_wdt_err_w	Watch dog timeout error from Traffic Generator when no write data is taken by the user interface. 当用户界面未获取写入数据时，流量生成器出现看门狗超时错误。
dbg_tg_compare_error	Sticky bit from the internal Traffic Generator asserted when a data error is found after calibration is completed. 当校准完成后发现数据错误时，来自内部流量生成器的粘性位被置1。
dbg_cmp_data_valid	Valid signal showing that the compare data from Traffic Generator is valid. 显示来自流量生成器的比较数据有效的有效信号。
dbg_cmp_error	Asserts when compare data is not matching the read data from User Interface. 当比较数据与从用户界面读取的数据不匹配时置1。
dbg_cmp_data_r	Register version of compare data from the Traffic Generator. 注册来自流量生成器的比较数据版本。
dbg_dq_error_bytelane_cmp	Indicates which byte has data comparison error for the Traffic Generator. 指示流量生成器的哪个字节有数据比较错误。
dbg_cumlative_dq_lane_error	Indicates which byte has data comparison error for the Traffic Generator. This is a sticky status signal and stays asserted until cleared manually using the dbg_clear_error. 指示流量生成器的哪个字节有数据比较错误。这是一个粘性状态信号，在使用dbg_clear_error手动清除之前一直保持置1状态。
dbg_cmp_addr_i	The start address of the burst for which the first data error occurred. 发生第一个数据错误的突发的起始地址。
dbg_cmp_bl_i	Burst length of the burst for which the first data error occurred. 发生第一个数据错误的突发的突发长度。
dbg_mcb_cmd_full_i	Memory Controller command FIFO full status when the first data error occurred发生第一个数据错误时，内存控制器命令FIFO满状态
dbg_mcb_wr_full_i	Memory Controller write data FIFO full status when the first data error occurred. 当发生第一个数据错误时，存储器控制器写入数据FIFO满状态。
dbg_mcb_rd_empty_i	Memory Controller read data FIFO empty status when the first data error occurred. 当第一个数据错误发生时，存储器控制器读取数据FIFO空状态。
dbg_ddrx_ila_rdpath_765_764[0]	Signifies PRBS Read Level Stage Start表示PRBS读级阶段开始
dbg_ddrx_ila_rdpath_765_764[1]	Signifies PRBS Read Level Stage Done表示PRBS读级阶段结束
dbg_wl_state_r	State variable for the Write Leveling State Machine. States can be decoded in the ddr_phy_wrlvl.v module. 写入均衡状态机的状态变量。可以在ddr_phy_wrlvl .v模块中解码。
dbg_dqs_cnt_r	Signifies the DQS byte group being calibrated during Write Leveling. The algorithm sequentially steps through the DQS byte groups until Write Leveling completes successfully or a data byte group fails due a 0 to 1 transition not being detected on DQ. 表示写入均衡期间校准的DQS字节组。该算法顺序逐步遍历DQ字节组，直到写入均衡成功完成，或者由于在DQ上未检测到0到1的转换而导致数据字节组失败。
dbg_wl_edge_detect_valid_r	Signifies valid time Write Leveling algorithm is searching for edge. 表示有效时间写入均衡算法正在搜索边缘。
dbg_rd_data_edge_detect_r_by_dqs	Signifies Write Leveling calibration found the 0 to 1 edge transition. 表示在0到1的边缘转换中找到了写水平校准。
Signal Name	Description

Table 1-74: DDR2/DDR3 Debug Signals (Cont’d)

dbg_wl_po_fine_cnt_by_dqs	PHASER_OUT Fine Taps found during Write Leveling. Byte capture based on VIO dbg_dqs setting. PHASER_OUT是写入均衡期间发现的精细抽头。基于VIO dbg_dqs设置的字节捕获。
dbg_wl_po_coarse_cnt_by_dqs	PHASER_OUT Coarse Taps found during Write Leveling. Byte capture based on VIO dbg_dqs setting. 在写入均衡期间发现相位器_OUT粗抽头。基于VIO dbg_dqs设置的字节捕获。
dbg_phy_oclkdelay_zfo	OCLKDELAY edge found indicator. {z2f, o2f, f2z, f2o}.在指示器中找到OCLKDELAY边沿。{z2f，o2f，f2z，f2o}。
dbg_ocal_fuzz2oneeighty	Stage 3 tap value of the left-edge of the fall window. 第3阶段：下降窗口左边缘的抽头值。
dbg_ocal_fuzz2zero	fuzz2zero Stage 3 tap value of the left-edge of the rise window. 上升窗口左边缘的fuzz2zero第3阶段抽头值。
dbg_ocal_oneeighty2fuzz	oneeighty2fuzz Stage 3 tap value of the right-edge of the fall window. 下降窗口右边缘的一个Eighty2Fuzz第3阶段抽头值。
dbg_ocal_zero2fuzz	Stage 3 tap value of the right-edge of the rise window. 上升窗口右边缘的第3阶段抽头值。
dbg_ocal_oclkdelay_calib_cnt	DQS group counter indicates which DQS group is in OCLKDELAY calibration. DQS组计数器指示哪个DQS群处于OCLK延迟校准中。
dbg_ocal_scan_win_not_found	Indicator that window is not found during OCLKDELAY calibration. 指示在OCLK延迟校准期间未找到窗口。
dbg_wrcal_pat_data_match_r	Asserts when the data pattern match is found during Write Calibration stage. 在写入校准阶段发现数据模式匹配时置1。
dbg_wrcal_pat_data_match_valid_r	Acts as a qualifier and asserts when the data pattern match is valid during Write Calibration stage. 当数据模式匹配在写入校准阶段有效时，用作限定符并置1。
dbg_wrcal_dqs_cnt_r	Current DQS group being calibrated in Write Calibration. When wrcal_start asserts, wrcal_dqs_cnt_r is 0. The algorithm sequentially steps through the DQS byte groups checking to see if the read data pattern matches the expected FF00AA5555AA9966 pattern. If the pattern matches, wrcal_dqs_cnt increments by 1. The algorithm then starts looking for the correct data pattern on the next byte until it reaches DQS_WIDTH – 1 or a data byte group fails due to the data pattern not being detected properly. The wrcal_dqs_cnt stays at DQS_WIDTH – 1 after wrcal_done signal is asserted. 写入校准中正在校准的当前DQS组。当wrcal_start置1时，wrcal _dqs_cnt_r为0。算法顺序遍历dqs字节组，检查读取的数据模式是否与预期的FF00AA55AA9966模式匹配。如果模式匹配，wrcal_dqs_cnt递增1。然后，算法开始在下一个字节上查找正确的数据模式，直到其达到dqs-WITH–1，或者由于未正确检测到数据模式，数据字节组失败。wrcal_done信号被置1后，wrcal-dqs-cnt保持在dqs_WITH–1。
cal2_state_r	Write Calibration state machine variable. States can be decoded in the ddr_phy_wrcal.v module. 将校准状态写入机器变量。可以在ddr_phy_wrcal .v模块中解码。
not_empty_wait_cnt	Count value during Write Calibration pattern detection. Maximum count is 0x1F. If count reaches 0x1F, write calibration fails with the assertion of dbg_wrcal_err. 写入校准模式检测期间的计数值。最大计数为0x1F。如果计数达到0x1F，则写入校准失败，并置1dbg_wrcal_err。
dbg_early1_data	Asserts when the pattern detected is one CK clock cycle early. When this is asserted, the Write Leveling algorithm moves the CK clock one cycle. After CK is moved, the Write Calibration algorithm restarts pattern detection. 当检测到的模式早一个CK时钟周期时置1。当这被置1时，写均衡算法将CK时钟移动一个周期。移动CK后，写入校准算法重新启动模式检测。
dbg_early2_data	Asserts when the pattern detected is two CK clock cycles early. When this is asserted, the Write Leveling algorithm moves the CK clock two cycles. After CK is moved, the Write Calibration algorithm restarts pattern detection. 当检测到的模式早两个CK时钟周期时置1。当这被置1时，写均衡算法将CK时钟移动两个周期。移动CK后，写入校准算法重新启动模式检测。
dbg_phy_oclkdelay_cal_57_54	Current DQS group being calibrated from OCLK_DELAY calibration stage. 当前DQS组正在从OCLK_DELAY校准阶段校准。
dbg_phy_wrlvl_128_75	PHASER_OUT Fine Taps found during Write Leveling for all bytes在所有字节的写均衡期间发现PHASER_OUT精细抽头
dbg_phy_wrlvl_155_129	PHASER_OUT Coarse Taps found during Write Leveling for all bytes. 在所有字节的写均衡期间发现的PHASER_OUT粗抽头。

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