赛灵思的DDR IP手册ug586翻译和学习（11）第十一章 PHASER_IN锁相校准故障

赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devices Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继续上一篇，翻译和学习的是调试PHASER_IN锁相校准故障。

P243

Debugging PHASER_IN PHASELOCKED Calibration Failures (dbg_pi_phaselock_err = 1)

调试PHASER_IN锁相校准故障（dbg_pi_phaselock_err=1）

Calibration Overview

During this stage of calibration, each PHASER_IN is placed in the read calibration mode to phase align its free-running frequency reference clock to the associated read DQS. The calibration logic issues back-to-back read commands to provide the PHASER_IN block with a continuous stream of DQS pulses for it to achieve lock. Each DQS has an associated PHASER_IN block. dbg_pi_phase_locked asserts when all PHASER_INs have achieved lock and the PHASER_INs are then placed in normal operation mode.

校准概述

在该校准阶段，每个PHASER_IN被置于读取校准模式，以将其自由运行频率参考时钟与相关的读取DQ相位对准。校准逻辑发出背对背读取命令，以向PHASER_IN块提供连续的DQS脉冲流。每个DQS具有相关的PHASER_ IN块。dbg_pi_phase_locked在所有PHASER_INs均已实现锁定且PHASER-INs随后被置于正常操作模式时断言。

Debug

If PHASER_IN PHASELOCKED calibration failed, probe the DQS at the memory. A continuous stream of DQS pulses must be seen for lock to occur. Verify the signal integrity of the DQS pulses.

调试

如果PHASER_IN锁相校准失败，则探测存储器中的DQS。必须看到连续的DQS脉冲流才能发生锁定。验证DQS脉冲的信号完整性。

Debugging PHASER_IN DQSFOUND Calibration Failures

(dbg_pi_dqsfound_err = 1)

调试DQS中的PHASER_IN发现校准故障

（dbg_pi_dqsfound_err=1）

Calibration Overview

In this stage of calibration, the different DQS groups in an I/O bank are aligned to the same PHY_Clk and the optimal read data offset position is found with respect to the read command. The calibration logic issues a set of four back-to-back reads with gaps in between. Each PHASER_IN detects the read DQS preamble. A single read data offset value is determined for all DQS groups in an I/O bank. The PHASER_OUT stage 2 delay for CK/Address/Command/Control byte lanes are increased and decreased to improve margin on the read DQS preamble detected. This read data offset is then used during read requests to the PHY_CONTROL block.

校准概述

在该校准阶段，I/O存储体中的不同DQS组对准同一PHY_Clk，并找到相对于读取命令的最佳读取数据偏移位置。校准逻辑发出一组四个背靠背读数，其间有间隙。每个PHASER_ IN检测读取的DQS前导码。为I/O存储体中的所有DQ组确定单个读取数据偏移值。增加和减少CK/Address/Command/Control字节通道的PHASER_ OUT阶段2延迟，以改善检测到的读取DQS前导码的裕度。然后在对PHY_ CONTROL块的读取请求期间使用该读取数据偏移。

Debug

• If the DQSFOUND stage fails, probe DQS at the memory. Sets of four back-to-back reads should be seen. Read DQS(s) is required by the PHASER_IN(s) to establish the read_data_offset value. If the design is stuck in the DQSFOUND stage, start observing the quality of DQS at the memory.

• Look at the read_data_offset values. There are two sets of read_data_offset values that need to be compared.

° To determine the read data offset found at the end of DQSFOUND calibration, look at dbg_rd_data_offset_0, dbg_calib_data_offset_1 (only when more than one bank is used), dbg_calib_data_offset_2 (only when three banks are used).

° To determine the data offset used during normal operation reads, look at dbg_data_offset, dbg_data_offset_1 (only when more than one bank is used), and dbg_data_ofset_2 (only when three banks are used).

– These signals change between reads, writes, and non-data commands. During writes, the value is CWL + 2 + slot#. During non-data commands, the value is 0. During reads, the value should match what was found during DQSFOUND calibration (dbg_rd_data_offset_0, dbg_rd_data_offset_1, and dbg_rd_data_offset_2).

调试

•如果DQSFOUND阶段失败，则在内存中探测DQS。应看到四组背靠背读取。PHASER_IN需要读取DQ来建立读取read_data_offset。如果设计停留在DQS发现阶段，则开始在内存中观察DQS的质量。

•查看read_data_offset值。需要比较两组read_data_offset值。

°要确定DQSFOUND校准结束时发现的读取数据偏移量，请查看dbg_rd_data_offset_0、dbg_ calib_DAT_OFFRET_1（仅当使用多个存储体时）、DBGUCALIB_data_OFFFET_2（仅在使用三个存储器时）。

°要确定正常操作读取期间使用的数据偏移，请查看dbg_data_offset、dbg_ data_ offset_1（仅当使用多个存储体时）和DBGuDAT_ofset_2（仅当三个存储器时）。

–这些信号在读、写和非数据命令之间变化。写入期间，值为CWL+2+插槽#。在非数据命令期间，值为0。在读取期间，该值应与DQSFOUND校准期间发现的值相匹配（dbg_rd_data_offset_0、dbg_ rd_data_OFFRET_1和dbg_rd_data_offset_2）。

• Compare the read data offset values used during calibration and normal operation reads. These values should match for reads with even CWL and be off by 1 for reads with odd CWL. One additional offset is added for odd CWL values because reads/writes are assigned to slot1 by the Memory Controller, whereas slot0 is used for even CWL.

• The read data offset should be equal to or greater than CL (Read Latency) + 4 or 5 memory cycles of round trip delay on the PCB. For DDR2 interfaces at lower frequencies, it is possible for read data offset to equal CL (Read Latency).

• The PHASER_OUT stage 2 delay for CK/Address/Command/Control byte lanes should also be observed for differences between passing and failing cases. The CK PHASER_OUT stage 2 delay can be observed in Vivado logic analyzer using the dbg_po_counter_read_val signal with dbg_pi_dqsfound_done as the trigger.

• When this stage fails (pi_dqsfound_err = 1), look to see if any of the dbg_calib_rd_data_offset/_1/_2 have calculated offsets. If not, focus on the DQS signals associated with the failing bank by probing each and analyzing the signal integrity.

If pi_dqsfound_err asserted, denoting a failure during DQSFOUND calibration, use pi_dqsfound_err = R as the trigger. If this stage completed successfully with the asserting of pi_dqsfound_done = 1, use pi_dqsfound_done = R as the trigger to analyze how the stage completed.

•比较校准和正常操作读取期间使用的读取数据偏移值。对于偶数CWL的读取，这些值应匹配，对于奇数CWL读取，应将其关闭1。为奇数CWL值添加一个附加偏移量，因为读/写由存储器控制器分配给slot1，而slot0用于偶数CWL。

•读取数据偏移量应等于或大于CL（读取延迟）+PCB上4或5个往返延迟存储器周期。对于较低频率的DDR2接口，读取数据偏移可能等于CL（读取延迟）。

如果pi_dqsfound_err被断言，表示DQSFOND校准期间出现故障，则使用pi_dQSFOUN_err=R作为触发器。如果此阶段在pi_dqsfound_done=1的断言下成功完成，则使用pi_dQSFOUN_DODE=R作为触发器来分析该阶段是如何完成的。