赛灵思的DDR IP手册ug586翻译和学习（12）第十二章 调试写均衡失败故障

赛灵思公司（Xilinx）的手册UG586：zynq-7000 AP Soc and 7 Series Devicevs Memory Interface Solutions，介绍的是DDR的IP核相关使用知识。我的阅读从第一章DDR3 and DDR2 SDRAM Memory Interface开始。继续上一篇，翻译和学习的是调试写均衡失败故障。

P246

Debugging Write Leveling Failures (dbg_wrlvl_err = 1)

Calibration Overview

Write leveling, a new feature in DDR3 SDRAMs, allows the controller to adjust each write DQS phase independently with respect to the CK forwarded to the DDR3 SDRAM device. This compensates for the skew between DQS and CK and meets the tDQSS specification. During this stage, the PHY logic asserts the Write_Calib_N input to the PHY Control block to indicate the start of write leveling. Periodic write requests are issued to the PHY Control block to generate periodic DQS pulses. The PHASER_IN outputs a free-running clock to capture the DQ feedback into the DQ IN_FIFOs. The PHASER_OUT fine and coarse taps are used to phase shift DQS one tap at a time until a 0-to-1 transition is seen on the feedback DQ.

Write Leveling is performed at three different points during the calibration process. After memory initialization completes, the PHASER_OUT fine and coarse taps are set to zero. Write Leveling is then initially performed to align DQS to CK. After OCLKDELAYED calibration completes, the coarse tap values found during the initial Write Leveling are carried over and the fine taps are reset to zero. Write Leveling is performed again to ensure the DQS-to-CK relationship is still correct.

Finally, during Write Calibration both the fine and coarse delays are carried over and final adjustments are made when necessary. During Write Calibration, the appropriate pattern must be detected. If Write Leveling aligned DQS to the wrong CK clock, final PHASER_OUT fine/coarse delay adjustments are required to move DQS up to two CK clock cycles. This section shows how to capture the Write Leveling results after each of these adjustments.

调试写均衡失败（dbg_wrlvl_err=1）

校准概述

写入均衡是

在校准过程中，在三个不同的点执行写入均衡。存储器初始化完成后，PHASER_OUT精细抽头和粗抽头设置为零。然后初始执行写入均衡以将DQ与CK对齐。在OCLK延迟校准完成后，在初始写入均衡期间发现的粗抽头值被转移，并且精细抽头被重置为零。再次执行写入均衡以确保DQS到CK关系仍然正确。

最后，在写入校准期间，精细延迟和粗延迟都会进行，并在必要时进行最终调整。在写入校准期间，必须检测适当的模式。如果写入均衡将DQ与错误的CK时钟对齐，则需要最终的PHASER_OUT精细/粗略延迟调整，以将DQ移动到两个CK时钟周期。本节显示了如何在每次调整后捕获写入均衡结果。

Debug

• Verify DQS is toggling on the board. The FPGA sends DQS during Write Leveling. If DQS is not toggling, something is wrong with the setup and the General Checks section of this answer record should be thoroughly reviewed.

• Verify fly-by-routing is implemented correctly on the board.

• Verify CK to DQS trace routing. The CK clocks should be longer than DQS. The recommended value for additional total electrical delay on CK/CK# relative to DQS/DQS# is 150 ps, but any value greater than 0 ps is acceptable.

• The Mode Registers must be properly set up to enable Write Leveling. Specifically, address bit A7 must be correct. If the part chosen in the MIG tool is not accurate or there is an issue with the connection of the address bits on the board, this could be an issue. If the Mode Registers are not set up to enable Write Leveling, the 0-to-1 transition is not seen.

Note: For dual rank design when address mirroring is used, address bit A7 is not the same between the two ranks.

• When dbg_wrlvl_err asserts (equals 1), users must determine during which of the three different stages write leveling is performed the failure occurred. Set the ILA trigger to dbg_wrlvl_err = R and look at the other “DDR Basic” signals to see which stages completed.

a. If only PHASELOCK and DQSFOUND completed, the write leveling failure occurred during the initial run through.

b. If dbg_wrcal_start did not assert, the write leveling failure occurred after OCLKDELAYED calibration.

c. If dbg_wrcal_start asserted but dbg_wrcal_done did not, the write leveling failure occurred during the final run through during Write Calibration.

• When dbg_wrlvl_done asserts (equals 1) and the results of each Write Leveling stage is of interest, separately use the following three ILA triggers to capture the Write

Leveling tap results for each stage. Seeing how Write Leveling completed is useful to see how far apart the taps are for different DQS byte groups.

a. dbg_wrlvl_done = R

b. dbg_wrcal_start = R

c. init_calib_complete = R

• To capture the write leveling results at each stage, change/increment dbg_dqs on the VIO and set the appropriate trigger as noted above. Look at the taps results and record in the “7 Series DDR3 Calibration Results” spreadsheet. Later releases of the MIG tool include results for all DQS byte groups removing the need to use dbg_dqs.

调试

•验证DQS是否在板上切换。FPGA在写入均衡期间发送DQ。如果DQS未切换，则说明设置有问题，应彻底检查此应答记录的“一般检查”部分。

•验证电路板上是否正确执行了飞行路线。

•验证CK至DQS跟踪路由。CK时钟应长于DQ。相对于DQS/DQS#，CK/CK#上的额外总电延迟的建议值为150 ps，但任何大于0 ps的值都是可接受的。

•模式寄存器必须正确设置，以启用写入均衡。具体而言，地址位A7必须正确。如果MIG工具中选择的零件不准确，或者电路板上的地址位连接存在问题，这可能是一个问题。如果模式寄存器未设置为启用写入均衡，则看不到0到1的转换。

注：对于使用地址镜像的双列设计，两个列之间的地址位A7不相同。

•当dbg_wrlvl_err断言（等于1）时，用户必须确定在三个不同阶段中的哪一个阶段执行写入均衡时发生了故障。将ILA触发器设置为dbg_wrlvl_err=R，并查看其他“DDR基本”信号，以查看哪些阶段已完成。

a、 如果只有PHASELOCK和DQSFind完成，则在初始运行期间发生写入调平故障。

b、 如果dbg_wrcal_start未断言，则在OCLK延迟校准后发生写入调平故障。

c、 如果dbg_wrcal_start被断言，但dbg_ wrcal _done未被断言，则在写入校准期间的最终运行期间发生写入均衡故障。

•当dbg_wrlvl_done断言（等于1）且每个写入均衡阶段的结果都值得关注时，分别使用以下三个ILA触发器捕获写入

每个阶段的调平抽头（Leveling tap）结果。查看写入均衡是如何完成的，有助于了解不同DQS字节组的抽头之间的距离。

a、 dbg_wrlvl_done=R

b、 dbg_wrcal_start=R

c、 init_calib_complete=R

•为了捕获每个阶段的写入均衡结果，改变/增加VIO上的dbg_dqs，并如上所述设置适当的触发器。查看taps结果并记录在“7系列DDR3校准结果”电子表格中。MIG工具的后续版本包括所有DQS字节组的结果，无需使用dbg_DQS。