赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(9)

读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍此IP的视频输出流接口。（ 这次的内容比较重要，涉及到IP输出的像素颜色格式）

P32

Video Output Stream Interface

The AXI4-Stream video interface supports dual or quad pixels per clock with 8 bits, 10 bits, 12 bits and 16 bits per component for RGB and YUV444 color spaces. The color depth in YUV422 color space is always 12-bits per pixel.

When the parameter, Max Bits Per Component, is set to 16, Figure 3-2 shows the data format for quad pixels per clock to be fully compliant with the AXI4-Stream video protocol. A data format for a fully compliant AXI4-Stream video protocol dual pixels per clock is illustrated in Figure 3-3.

视频输出流接口

AXI4流视频接口支持每个时钟的双像素或四像素，RGB和YUV444颜色空间的每个分量有8位、10位、12位和16位。YUV422颜色空间中的颜色深度始终为每像素12位。

当参数Max Bits Per Component设置为16时，图3-2显示了完全符合AXI4 Stream视频协议的每时钟四像素数据格式。图3-3显示了完全符合AXI4流视频协议双像素时钟的数据格式。

When the parameter, Max Bits Per Component, is set to 12, video formats with actual bits per component larger than 12 is truncated to the Max Bits Per Component. The remaining least significant bits are discarded. If the actual bits per component is smaller than Max Bits Per Component set in the Vivado IDE, all bits are transported with the MSB aligned and the remaining LSB bits are padded with 0. This applies to all Max Bits Per Component settings.

当参数“每个组件的最大位数”设置为12时，每个组件的实际位数大于12的视频格式将被截断为每个组件的最高位数。剩余的最低有效位被丢弃。如果每个组件的实际位小于Vivado IDE中设置的“每个组件的最大位”，则所有位都将与MSB对齐，其余LSB位用0填充。这适用于所有“每个组件最大位”设置。

Table 3‐1: Max Bits Per Component Support

As an illustration, when Max Bits Per Component is set to 12, Figure 3-4 shows the data format for quad pixels per clock to be fully compliant with the AXI4-Stream video protocol.
如图所示，当每个组件的最大比特数设置为12时，图3-4显示了每个时钟四像素的数据格式，以完全符合AXI4流视频协议。

The video interface can also transport quad and dual pixels in the YUV420 color space. However the current data format is not complaint with the AXI4-Stream video protocol. Figure 3-6 and Figure 3-7 show the data format for quad and dual pixels formats.

视频接口还可以在YUV420颜色空间中传输四像素和双像素。然而，当前的数据格式并不符合AXI4流视频协议。图3-6和图3-7显示了四像素和双像素格式的数据格式。

Similarly, for YUV 4:2:0 deep color (10, 12, or 16 bits), the data representation is the same as shown in Figure 3-6 and Figure 3-7. The only difference is that each component carries more bits (10, 12, and 16). To make the YUV 4:2:0 compatible with AXI4-Stream Video IP and System Design Guide [Ref 12], enable it from the HDMI Receiver Subsystem GUI.

Using an 8-bit video as an example, Figure 3-8 illustrates the YUV 4:2:0 AXI4-Stream video data representation in AXI4-Stream Video IP and System Design Guide [Ref 12]

类似地，对于YUV 4:2:0深颜色（10、12或16位），数据表示与图3-6和图3-7所示相同。唯一的区别是每个组件携带更多位（10、12,16）。要使YUV 4:2:0与AXI4流视频IP和系统设计指南[参考12]兼容，请从HDMI接收器子系统GUI启用它。

以8位视频为例，图3-8说明了AXI4流视频IP和系统设计指南中的YUV 4:2:0 AXI4视频数据表示[Ref 12]

However, in the native HDMI video interface, the video data representation must be as shown in Figure 3-9.

然而，在本机HDMI视频接口中，视频数据表示必须如图3-9所示。

Therefore, a remapping feature is added to HDMI 1.4/2.0 Receiver Subsystem to convert AXI4-Stream video into HDMI native video.

The subsystem provides full flexibility to construct a system using the configuration parameters, maximum bits per component and number of pixels per clock. Set these parameters so that the video clock and link clock are supported by the targeted device. For example, when dual pixels per clock is selected, the AXI4-Stream video need to run at higher clock rate comparing with quad pixels per clock design. In this case, it is more difficult for the system to meeting timing requirements. Therefore the quad pixels per clock data mapping is recommended for design intended to send higher video resolutions.

Some video resolutions (for example, 720p60) have horizontal timing parameters (1650) which are not a multiple of 4. In this case the dual pixels per clock data mapping must be chosen. For more information on the video AXI4-Stream interface and video data format, see the AXI4-Stream Video IP and System Design Guide (UG934) [Ref 12]