赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(3)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(3)

读赛灵思IP手册,HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide,即HDMI接受器系统的手册。本期介绍Audio Clock Regeneration Signals 音频时钟再生信号、DDC显示数据通道、热插拔检测和信息框架。

P9 Audio Clock Regeneration Signals

Audio Clock Regeneration Signals

The subsystem can output Audio Clock Regeneration (ACR) signals that allow receiver audio peripherals to regenerate the audio clock.

音频时钟再生信号

子系统可以输出音频时钟再生(ACR)信号,允许接收器音频外围设备再生音频时钟。

The audio clock regeneration architecture is not part of the HDMI RX subsystem. You must provide an audio clock to the application. This can be achieved by using an internal PLL or external clock source, depending on the audio clock requirements, audio sample frequency and jitter. When HDMI TX subsystem is used in DVI mode, the ACR inputs are ignored. You can decide to leave them open or connect them to some fix values (for example, connecting acr_cts, acr_n, and acr_valid to 0). When HDMI RX subsystem is used in DVI mode, the ACR outputs can be left unconnected. See Chapter 5, Example Design for an example ACR module that is part of the audio pattern generation system.

音频时钟再生架构不是HDMI RX子系统的一部分。您必须为应用程序提供音频时钟。这可以通过使用内部PLL或外部时钟源来实现,具体取决于音频时钟要求、音频采样频率和抖动。当HDMI TX子系统在DVI模式下使用时,ACR输入被忽略。您可以决定让它们保持打开状态,或者将它们连接到一些固定值(例如,将acr_ctsacr_nacr_valid连接到0)。当HDMI RX子系统在DVI模式下使用时,ACR输出可以保持未连接状态。参见第5章示例设计,了解作为音频模式生成系统一部分的ACR模块示例。

Display Data Channel (DDC)

The subsystem allows the end-user to build an HDMI sink device, which negotiates with the targeted HDMI source device for supported features and capabilities. The communication between the source device(s) and the sink device is implemented through the DDC lines, which is an I2C bus included on the HDMI cable.

显示数据通道(DDC

该子系统允许最终用户构建HDMI接收器设备,该设备与目标HDMI源设备协商支持的特性和功能。源设备和接收器设备之间的通信通过DDC线路实现,DDC线路是HDMI电缆上包含的I2C总线。

Hot Plug Detect

The subsystem supports the Hot Plug Detect (HPD) feature, which is a communication mechanism between HDMI source and HDMI sink devices. For example, when an HDMI cable is inserted between the HDMI source and HDMI sink devices, the cable-detect signal is asserted. The subsystem then outputs a hpd signal, which triggers the start of a communication between the source device and sink device.

热插拔检测

子系统支持热插拔检测(HPD)功能,这是HDMI源设备和HDMI接收器设备之间的通信机制。例如,当HDMI电缆插入HDMI源设备和HDMI接收器设备之间时,将断言电缆检测信号。然后,子系统输出hpd信号,该信号触发源设备和接收器设备之间的通信开始。

InfoFrames

There are two basic InfoFrames expected in any HDMI system, which are Auxiliary Video Information (AVI) Infoframe and Audio Infoframe. An InfoFrame is structured with a 4-byte header and 32-byte data (payload). All InfoFrames types are described in detail in CEA-861-F.

信息框架

任何HDMI系统都需要两个基本信息帧,即辅助视频信息(AVI)信息帧和音频信息帧。InfoFrame由一个4字节的头和32字节的数据(有效负载)组成。CEA-861-F中详细描述了所有信息帧类型。

In the HDMI RX Subsystem driver, there is a generic API function for you to retrieve the InfoFrame. This is an example of a function call:

HDMI RX子系统驱动程序中,有一个通用的API函数供您检索InfoFrame。以下是函数调用的示例:

u8 AuxBuffer[36];

memcpy(AuxBuffer, XV_HdmiRxSs_GetAuxiliary(&HdmiRxSsPtr), sizeof(AuxBuffer));

HdmiRxSsPtr is a pointer to the HDMI RX Subsystem, and AuxBuffer is a local buffer allocated to store the AUX InfoFrame header and payload data.

HdmiRxSsPtr是指向HDMI RX子系统的指针,AuxBuffer是分配用于存储AUX InfoFrame头和有效负载数据的本地缓冲区。

Figure 2-4 a graphically represents an HDMI Infoframe structure, which is one type of HDMI data island packet. For HDMI, all data island packets consist of a 4-byte packet header and a 32 bytes of packet contents. The packet header contains 24 data bits (3 bytes) and 8 bits (1 byte) of BCH ECC parity.

2-4a以图形方式表示HDMI信息帧结构,它是HDMI数据岛包的一种类型。对于HDMI,所有数据岛数据包都由4字节数据包头和32字节数据包内容组成。数据包头包含24个数据位(3字节)和8BCH ECC奇偶校验位(1字节)。

图片[1]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(3)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

The packet body, graphically represented in Figure 2-5, is made from four subpackets; each subpacket includes 56 bits (7 bytes) of data and 8 bits (1 byte) of BCH ECC parity.

2-5所示的包体由四个子包组成;每个子包包括56位(7字节)数据和8位(1字节)BCH ECC奇偶校验。

图片[2]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(3)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

Notes:

1. ECC is calculated in HDMI 1.4/2.0 Receiver Subsystem core. Therefore, must construct HB0…HB2, and PB0, PB1…PB26, PB27 according to HDMI specs in the software.

2. When calculating the checksum value (PB0), the ECC values are ignored.

Refer to section 5.2.3.4 and 5.2.3.5 of the HDMI 1.4 Specification [Ref 10] for more information on the InfoFrame structure.

 

 

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