赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(5)

读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍此IP的端口描述和CPU接口。

P13

Resource Utilization

For full details about performance and resource utilization, visit the Performance and Resource Utilization web page.

资源利用率

有关性能和资源利用率的完整详细信息，请访问性能和资源使用率网页。

Port Descriptions

Figure 2-7 to Figure 2-10 show the HDMI 1.4/2.0 Receiver Subsystem ports when AXI4-Stream is selected as video interface. The VIDEO_OUT port is expanded in the figure to show the detail AXI4-Stream Video bus signals.

The following subsystem has three default interfaces:

• AXI4-Lite control interface (S_AXI_CPU_IN)

• Video Interface (VIDEO_IN)

• Audio Interface (AUDIO_IN)

端口描述

图2-7至图2-10显示了选择AXI4流作为视频接口时的HDMI 1.4/2.0接收器子系统端口。图中扩展了VIDEO_OUT端口，以显示AXI4流视频总线信号的详细信息。

以下子系统有三个默认接口：

•AXI4 Lite控制接口（S_AXI_CPU_IN）

•视频接口（Video_IN）

•音频接口（Audio_IN）

Figure 2-11 to Figure 2-14 show the HDMI 1.4/2.0 Receiver Subsystem ports when Native Video is selected as video interface. The VIDEO_OUT port is expanded in the figure to show the detail Native Video bus signals.

图2-11至图2-14显示了选择Native Video作为视频接口时的HDMI 1.4/2.0接收器子系统端口。图中扩展了VIDEO_OUT端口，以显示本机视频总线信号的详细信息。

P22

CPU Interface
Table 2-1 shows the AXI4-Lite control interface signals. This interface is an AXI4-Lite interface and runs at the s_axi_cpu_aclk clock rate. Control of the subsystem is only supported through the subsystem driver.
IMPORTANT: The direct register level access to any of the submodules is not supported. Instead, all the accesses are done through driver APIs.

CPU接口

表2-1显示了AXI4 Lite控制接口信号。此接口是AXI4 Lite接口，以s_axi_cpu_aclk时钟频率运行。仅通过子系统驱动程序支持对子系统的控制。

重要提示：不支持对任何子模块的直接寄存器级访问。相反，所有访问都是通过驱动程序API完成的。

Table 2‐1: CPU Interface Ports

Video Output Stream Interface
This HDMI 1.4/2.0 Receiver Subsystem is supporting two types of video output stream interfaces, which eventually is mapped to HDMI 1.4/2.0 Receiver Subsystem VIDEO_OUT interface.
• AXI4-Stream Video interface
• Native Video Interface
Table 2-2 shows the signals for AXI4-Stream video output streaming interface. This interface is an AXI4-Stream master interface and runs at the s_axis_video_aclk clock rate. The data width is user-configurable in the Vivado IDE by setting Max Bits Per Component (BPC) and Number of Pixels Per Clock on Video Interface (PPC).

视频输出流接口

此HDMI 1.4/2.0接收器子系统支持两种类型的视频输出流接口，最终映射到HDMI 1.4/20接收器子系统video_OUT接口。

•AXI4流视频接口

•本机视频接口

表2-2显示了AXI4流视频输出流接口的信号。此接口是AXI4流主接口，以s_axis_video_aclk时钟频率运行。用户可以在Vivado IDE中通过设置每个组件的最大位数（BPC）和视频接口（PPC）上每个时钟的像素数来配置数据宽度。

Native Video Output Interface
Table 2-3 shows the signals for Native video output interface. This interface is a standard video interface and runs at video_clk clock rate. The data width is user-configurable in the Vivado IDE by setting Max Bits Per Component (BPC) and Number of Pixels Per Clock on Video Interface (PPC).

本机视频输出接口

表2-3显示了Native视频输出接口的信号。此接口是标准视频接口，以video_clk时钟速率运行。用户可以在Vivado IDE中通过设置每个组件的最大位数（BPC）和视频接口（PPC）上每个时钟的像素数来配置数据宽度。

Table 2‐2: Video Output Stream Interface

Table 2‐3: Native Video Output Interface