赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(6)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(6)

读赛灵思IP手册,HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide,即HDMI接受器系统的手册。本期介绍此IP的音频输出流接口。

Audio Output Stream Interface

Table 2-4 shows the signals for AXI4-Stream audio output streaming interfaces. The audio interface transports 24-bits audio samples in the IEC 60958 format. A maximum of eight channels are supported. The audio interface is a 32-bit AXI4-Stream master interface and runs at the s_axis_audio_aclk clock rate.

音频输出流接口

2-4显示了AXI4流音频输出流接口的信号。音频接口以IEC 60958格式传输24位音频样本。最多支持八个通道。音频接口是32AXI4流主接口,以s_axis_audio_ackk时钟频率运行。

Table 24: Audio Output Stream Interface

Name

Direction

Width

Description

s_axis_audio_aclk  

Input

1

Clock (The audio  streaming clock must be greater than or equal or greater than 128 times the  audio sample frequency)

s_axis_audio_aresetn  

Input

1

Reset  (Active-Low)

AUDIO_OUT_tdata

Output

32

Data
[31] P (Parity)
[30] C (Channel status)
[29] U (User bit)
[28] V (Validity bit)
[27:4] Audio sample word
[3:0] Preamble code
4’b0001 Subframe 1/start of audio block
4’b0010 Subframe 1
4’b0011 Subframe 2

AUDIO_OUT_tid

Output

3

Channel ID

AUDIO_OUT_tready  

Input

1

Ready

AUDIO_OUT_tvalid  

Output

1

Valid

Audio Clock Regeneration Interface

The audio clock regeneration (ACR) interface has a Cycle Time Stamp (CTS) parameter vector and an Audio Clock Regeneration Value (N) parameter vector. Both vectors are 20 bits wide. The valid signal is driven High when the CTS and N parameters are stable. For more information, see Chapter 7 of the HDMI 1.4 specification [Ref 10].

音频时钟再生接口

音频时钟再生(ACR)接口有一个周期时间戳(CTS)参数矢量和一个音频时钟再生值(N)参数矢量。两个矢量都是20位宽。当CTSN参数稳定时,有效信号被驱动为高电平。有关更多信息,请参阅HDMI 1.4规范第7[参考文献10]

The subsystem should set up the CTS and N parameters before asserting the valid signal.

Table 2-5 shows the Audio Clock Regeneration (ACR) interface signals. This interface runs at the s_axis_audio_aclk clock rate.

子系统应在断言有效信号之前设置CTSN参数。

2-5显示了音频时钟再生(ACR)接口信号。此接口以s_axis_audio_ackk时钟频率运行。

Table 25: Audio Clock Regeneration (ACR) Interface

Name

Direction

Width

Description

acr_cts

Output

20

CTS

acr_n

Output

20

N

acr_valid

Output

1

Valid

HDMI Link Input Interface

Table 2-6 shows the HDMI Link Input interface signals. This interface runs at the link_clk clock rate.

HDMI链路输入接口

2-6显示了HDMI链路输入接口信号。此接口以link_clk时钟频率运行。

Table 26: HDMI Link Input Interface

Name

Direction

Width

Description

link_clk

Input

1

Link clock

LINK_DATA0_IN_tdata  

Input

40

Link data 0

LINK_DATA0_IN_tvalid  

Input

1

Link Data 0  Valid

LINK_DATA1_IN_tdata  

Input

40

Link data 1

LINK_DATA1_IN_tvalid  

Input

1

Link Data 1  Valid

LINK_DATA2_IN_tdata  

Input

40

Link data 2

LINK_DATA2_IN_tvalid  

Input

1

Link Data 2  Valid

 

 

 

请登录后发表评论

    没有回复内容