赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(7)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(7)

读赛灵思IP手册,HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide,即HDMI接受器系统的手册。本期介绍此IP的HDCP 输入接口、热插拔、时钟和复位。

P26

HDCP 1.4 Key Input Interface (AXI4-Stream Slave Interface)

Table 2-8 shows the signals for HDCP 1.4 key interface. This interface runs at the hdcp14_key_aclk.

HDCP 1.4键输入接口(AXI4流从接口)

2-8显示了HDCP 1.4键接口的信号。此接口在hdcp14_key_aclk上运行。

Table 28: HDCP 1.4 Key Input Interface

Name

Direction

Width

Description

HDCP_KEY_IN_tdata  

Input

64

HDCP 1.4 key  data

HDCP_KEY_IN_tlast  

Input

1

End of key data

HDCP_KEY_IN_tready  

Output

1

Ready

HDCP_KEY_IN_tuser  

Input

8

Start of key  data

HDCP_KEY_IN_tvalid  

Input

1

Valid

hdcp14_key_aclk

Output

1

AXI4-Stream  clock

hdcp14_key_aresetn  

Output

1

Reset  (Active-Low)

hdcp14_start_key_transmit  

Output

1

Start key  transmit

hdcp14_reg_key_sel  

Output

3

Key select

hdcp14_irq

Output

1

HDCP 1.4  interrupt

hdcp14_timer_irq  

Output

1

HDCP 1.4 timer  interrupt

For the HDCP 1.4 receiver, an HDCP Key Management module is needed, which is able to send keys over the AXI4-Stream interface to the HDCP 1.4 controller. Figure 2-15 shows an example of how the HDMI RX Subsystem is connected to the HDCP Key Management module through a Key Management Bus (AXI4-Stream). The HDCP Key Management module is not part of the HDMI RX Subsystem. For HDCP 1.4 design details, see the HDCP v1.4 Product Guide (PG224) [Ref 24]

对于HDCP 1.4接收机,需要一个HDCP密钥管理模块,该模块能够通过AXI4 Stream接口将密钥发送到HDCP 1.4控制器。图2-15显示了HDMI RX子系统如何通过密钥管理总线(AXI4流)连接到HDCP密钥管理模块的示例。HDCP密钥管理模块不是HDMI RX子系统的一部分。有关HDCP 1.4设计的详细信息,请参阅HDCP 1.4版产品指南(PG224[参考文献24]

However, the HDCP 2.2 key is handled slightly differently as it is solely controlled by the software application. The user application is responsible for providing the infrastructure to securely store and retrieve the keys to be loaded into the HDCP 2.2 drivers. For the detailed list of keys that are required to be loaded by the user application, see the HDCP v2.2 Product Guide (PG249) [Ref 23].

然而,HDCP 2.2键的处理方式略有不同,因为它完全由软件应用程序控制。用户应用程序负责提供基础设施,以安全地存储和检索要加载到HDCP 2.2驱动程序中的密钥。有关用户应用程序需要加载的密钥的详细列表,请参阅HDCP v2.2产品指南(PG249[参考文献23]

HDCP 2.2 Interrupt Outputs

Table 2-9 shows the signals for HDCP 2.2 interrupt output ports.

HDCP 2.2中断输出

2-9显示了HDCP 2.2中断输出端口的信号。

Table 29: HDCP 2.2 Interrupt Output Interface

Name

Direction

Width

Description

hdcp22_irq

Output

1

HDCP 2.2  interrupt

hdcp22_timer_irq  

Output

1

HDCP 2.2 timer  interrupt

Miscellaneous Signals with AXI4-Stream Video Interface

Table 2-10 shows the miscellaneous signals with AXI4-Stream video interface selected.

AXI4流视频接口的其他信号

2-10显示了选择AXI4流视频接口的其他信号。

Table 210: Miscellaneous Signals with AXI4-Stream Video Interface

Name

Direction

Width

Description

hpd

Output

1

If XGUI option:  Hot Plug Detect Active High (Default)
0 – Hot Plug Detect is released
1 – Hot Plug Detect is asserted
If XGUI option: Hot Plug Detect Active Low
(1)
0 – Hot Plug Detect is asserted
1 – Hot Plug Detect is released

cable_detect

Input

1

If XGUI option:  Cable Detect Active High (Default)
0 – Cable Detect is released
1 – Cable Detect is asserted
If XGUI option: Cable Detect Active Low
(2)
0 – Cable Detect is asserted
1 – Cable Detect is released

irq

Output

1

Interrupt  request for CPU. Active-High.

video_clk

Input

1

Reference Native  Video Clock
When AXI4-Stream is selected as Video Interface, a Video
In to AXI4-Stream Bridge module is added to the HDMI RX
Subsystem to convert Native Video into AXI4-Stream
Video. HDMI RX core uses this video_clk to clock out the
Video Data.

SB_STATUS_IN_tdata  

Input

2

Side Band Status  input signals
Bit 0: link_rdy
Bit 1: video_rdy

SB_STATUS_IN_tvalid  

Input

1

Side Band Status  input valid

fid

Output

1

Field ID for  AXI4-Stream bus. Used only for interlaced
video.
0 – even field
1 – odd field
For progress video the output is always Low.

1. The Hot Plug Detect (HPD) signal is driven by an HDMI sink and asserted when the HDMI cable is connected to notify the HDMI source of the presence of an HDMI sink. When designing a HDMI sink system using HDMI Receiver Subsystem, in the PCB, if you choose to use a voltage level shifter, the HPD polarity remains as Active High.

However, if you choose to add an inverter to the HPD signal, then the HPD polarity must be set to Active Low in HDMI Receiver Subsystem GUI. There are two common ways of using HPD: Toggle HPD to trigger HDCP authentication process (usually 100 ~ 500ms). Or a longer HPD toggle (>1s), the HDMI sink is notifying the source its present without cable unplug and plug. The software API used to assert and release HPD is XV_HdmiRxSs_SetHpd.

2. The Cable Detect signal is connected to a 5V power signal from the HDMI cable connector via some level shifter to notify the HDMI RX Subsystem that a HDMI source is connected.

1.热插拔检测(HPD)信号由HDMI接收器驱动,并在连接HDMI电缆以通知HDMI源存在HDMI接收器时断言。使用HDMI接收器子系统设计HDMI接收器系统时,在PCB中,如果选择使用电压电平移位器,HPD极性将保持为高电平有效。

但是,如果您选择向HPD信号添加逆变器,则必须在HDMI接收器子系统GUI中将HPD极性设置为低电平有效。有两种常用的使用HPD的方法:切换HPD以触发HDCP身份验证过程(通常为100~500ms)。或者使用更长的HPD切换(>1s),HDMI接收器将通知源其存在,而无需拔下电缆和插头。用于断言和发布HPD的软件APIXV_AdmiRxSs_SetHpd

2.电缆检测信号通过一些电平移位器连接到来自HDMI电缆连接器的5V电源信号,以通知HDMI RX子系统已连接HDMI源。

Miscellaneous Signals with Native Video Interface

Table 2-11 shows the miscellaneous signals with native video interface selected.

Table 211: Miscellaneous Signals with Native Video Interface

Name

Direction

Width

Description

hpd

Input

1

If XGUI option:  Hot Plug Detect Active High (Default)
0 – Hot Plug Detect is released
1 – Hot Plug Detect is asserted
If XGUI option: Hot Plug Detect Active Low
(1)
0 – Hot Plug Detect is asserted
1 – Hot Plug Detect is released

cable_detect

Input

1

If XGUI option:  Cable Detect Active High (Default)
0 – Cable Detect is released
1 – Cable Detect is asserted
If XGUI option: Cable Detect Active Low
(2)
0 – Cable Detect is asserted
1 – Cable Detect is released

irq

Output

1

Interrupt  request for CPU. Active-High.

SB_STATUS_IN_tdata  

Input

2

Side Band Status  input signals
Bit 0: link_rdy
Bit 1: video_rdy

SB_STATUS_IN_tvalid  

Input

1

Side Band Status  input valid

video_rst

Output

1

Video reset  signal in video_clk domain. Active-High.

1. The Hot Plug Detect (HPD) signal is driven by an HDMI sink and asserted when the HDMI cable is connected to notify the HDMI source of the presence of an HDMI sink. In most cases, the HDMI sink is simply connected to 5V power signal. Therefore, in the PCB, if you choose to use a voltage divider or level shifter, the HPD polarity remains as Active High. However, if you add an inverter to the HPD signal, then the HPD polarity must be set to Active Low in HDMI Transmitter Subsystem GUI. When designing a HDMI sink system using HDMI Receiver Subsystem, in the PCB, if you choose to use a voltage level shifter, the HPD polarity remains as Active High. However, if you choose to add an inverter to the HPD signal, then the HPD polarity must be set to Active Low in HDMI Receiver Subsystem GUI. There are two common ways of using HPD: Toggle HPD to trigger HDCP authentication process (usually 100 ~ 500ms). Or a longer HPD toggle (>1s), the HDMI sink is notifying the source its present without cable unplug and plug. The software API used to assert and release HPD is XV_HdmiRxSs_SetHpd.

2. The Cable Detect signal is connected to a 5V power signal from the HDMI cable connector via some level shifter to notify the HDMI RX Subsystem that a HDMI source is connected.

1.热插拔检测(HPD)信号由HDMI接收器驱动,并在连接HDMI电缆以通知HDMI源存在HDMI接收器时断言。在大多数情况下,HDMI接收器只需连接到5V电源信号。因此,在PCB中,如果选择使用分压器或电平移位器,HPD极性将保持为高电平有效。但是,如果您向HPD信号添加逆变器,则必须在HDMI发射机子系统GUI中将HPD极性设置为低电平有效。使用HDMI接收器子系统设计HDMI接收器系统时,在PCB中,如果选择使用电压电平移位器,HPD极性将保持为高电平有效。但是,如果您选择向HPD信号添加逆变器,则必须在HDMI接收器子系统GUI中将HPD极性设置为低电平有效。有两种常用的使用HPD的方法:切换HPD以触发HDCP身份验证过程(通常为100~500ms)。或者使用更长的HPD切换(>1s),HDMI接收器将通知源其存在,而无需拔下电缆和插头。用于断言和发布HPD的软件APIXV_AdmiRxSs_SetHpd

2.电缆检测信号通过一些电平移位器连接到来自HDMI电缆连接器的5V电源信号,以通知HDMI RX子系统已连接HDMI源。

P30 clock and reset

Clocks and Resets

Table 2-12 provides an overview of the clocks and resets. See Clocking and Resets in Chapter 3 for more information.

时钟和复位

2-12概述了时钟和复位。有关更多信息,请参阅第3章中的时钟和复位。

Table 212: Clocks and Resets

Name

Direction

Width

Description

s_axi_cpu_aclk

Input

1

AXI4-Lite CPU  control interface clock.

s_axi_cpu_aresetn  

Input

1

Reset,  associated with s_axi_cpu_aclk
(active-Low). The s_axi_cpu_aresetn signal
resets the entire subsystem including the data
path and AXI4-Lite registers.

s_axis_video_aclk  

Input

1

AXI4-Stream  video output clock.

s_axis_video_aresetn  

Input

1

Reset,  associated with s_axis_video_aclk
(active-Low). Resets the AXI4-Stream data path
for the video output.

s_axis_audio_aclk  

Input

1

AXI4-Stream  Audio output clock. (The audio
streaming clock must be greater than or equal
to 128 times the audio sample frequency)

s_axis_audio_aresetn  

Input

1

Reset,  associated with s_axis_audio_aclk
(active-Low). Resets the AXI4-Stream data path
for the audio output.

link_clk

Input

1

HDMI Link data  output clock. This connects to
the Video PHY Controller Link clock output.

video_clk

Input

1

Clock for the  native video interface.

 

 

 

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