赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(8)

读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍此IP的一般设计指南和音频数据流。

P31 开启新的一章

Designing with the Subsystem

This chapter includes guidelines and additional information to facilitate designing with the subsystem.

使用子系统进行设计

本章包括指导原则和其他信息，以便于子系统的设计。

General Design Guidelines

The subsystem connects to other hardware components to construct a complete HDMI RX system. These hardware components usually are different from device to device. For example, Kintex®-7 devices have a different PLL architecture from UltraScale™ devices.

Therefore, you need to fully understand the system and adjust the subsystem parameters accordingly. Appendix C, Application Software Development describes how to integrate the subsystem API into a software application.

一般设计指南

该子系统与其他硬件组件相连，构成一个完整的HDMI RX系统。这些硬件组件通常因设备而异。例如，Kintex®-7设备具有与UltraScale不同的PLL架构™设备。

因此，您需要充分了解系统并相应地调整子系统参数。附录C“应用软件开发”描述了如何将子系统API集成到软件应用程序中。

Audio Data Stream

An AXI4-Stream audio cycle is illustrated in Figure 3-1. The data is valid when both the valid (TVLD) and ready (TRDY) signals are asserted. The HDMI 1.4/2.0 Receiver Subsystem sends out adjacent channels in sequential order (CH0, CH1, etc). Usually, the audio stream receiver also expects the channels in sequential order. If the channel data is not in order, the channel data might be mapped into other channel sample slots.

音频数据流

AXI4流音频周期如图3-1所示。当有效（TVLD）和就绪（TRDY）信号都被断言时，数据有效。HDMI 1.4/2.0接收器子系统按顺序发送相邻通道（CH0、CH1等）。通常，音频流接收器也期望通道按顺序排列。如果通道数据不正常，则可能会将通道数据映射到其他通道示例窗。

In HDMI 1.4/2.0 Receiver Subsystem, the number of Audio Channels is set through the software driver. You must enable the correct number of audio channel according to your use case and send the corresponding audio channel data mapping to the channel ID (TID). For example, if you intend to send out 8 channel audio, then you must set Audio Channel number to 8 in HDMI 1.4/2.0 Receiver Subsystem driver. Then, the corresponding audio data must be prepared and sent to HDMI 1.4/2.0 Receiver Subsystem in the hardware, as described in Figure 3-1.