赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(10)

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读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍此IP的clocking时钟。

P36

Clocking

The S_AXI_CPU_IN, VIDEO_IN, and AUDIO_IN can be run at their own clock rate. The HDMI link interfaces and native video interface also run at their own clock rate. Therefore, five separate clock interfaces are provided called s_axi_cpu_aclk, s_axis_video_aclk, s_axis_audio_aclk, link_clk, and video_clk respectively.

The audio streaming clock must be greater than or equal to 128 times the audio sample frequency. Because audio clock regeneration is not part of the HDMI RX subsystem, you must provide an audio clock to the application. This can be achieved by using an internal PLL or external clock source.

IMPORTANT: The AXI4-Lite CPU clock must run at 100 Mhz.

时钟

S_AXI_CPU_IN、VIDEO_IN和AUDIO_IN可以以各自的时钟频率运行。HDMI链路接口和本机视频接口也以各自的时钟频率运行。因此，提供了五个单独的时钟接口，分别称为s_axi_cpu_aclk、s_axis_video_aclk，s_axis_audio_aclk、link_clk和video_clk。

音频流时钟必须大于或等于音频采样频率的128倍。由于音频时钟再生不是HDMI RX子系统的一部分，您必须为应用程序提供音频时钟。这可以通过使用内部PLL或外部时钟源来实现。

重要事项：AXI4 Lite CPU时钟必须以100 Mhz的频率运行。

The HDMI clock structure is illustrated in Figure 3-10 and Table 3-2.

Table 3‐2: Clocking

HDMI Clocking
Clock	Function	Freq/Rate	Example(1)
TMDS clock	Source synchronous clock to HDMI interface (This is the actual clock on the HDMI cable).	= 1/10 data rate (for data rates < 3.4 Gb/s) = 1/40 data rate (for data rates > 3.4 Gb/s)	Data rate = 2.97 Gb/s TMDS clock = 2.97/10 = 297 MHz Data rate = 5.94 Gb/s TMDS clock = 5.94/40 = 148.5 MHz
Data clock	This is the actual data rate clock. This clock is not used in the system. It is only listed to illustrate the clock relations.	= TMDS clock (for data rates < 3.4 Gb/s) = TMDS clock * 4 (for data rates > 3.4 Gb/s)	Data rate = 2.97 Gb/s Data clock = TMDS clock * 1 = 297 MHz Data rate = 5.94 Gb/s Data clock = TMDS clock * 4 = 594 MHz TMDS clock = 148.5MHz
Link clock	Clock used for data interface between HDMI PHY Layer Module and subsystem	= 1/4 of data clock	TMDS clock = 297 MHz Data clock = 297 MHz Link clock = 297 MHz/4 = 74.25 MHz Data clock = 594 MHz Link clock = 594 MHz/4 = 148.5 MHz
Pixel clock	This is the internal pixel clock. This clock is not used in the system. It is only listed to illustrate the clock relations	for 8 bpc pixel clock = data clock for 10 bpc pixel clock = data clock/1.25 for 12 bpc pixel clock = data clock/1.5 for 16 bpc pixel clock = data clock/2
Video clock	Clock used for video interface	for dual pixel video clock = pixel clock/2 for quad pixel video clock = pixel clock/4	297 MHz/2 = 148.5 MHz for dual pixel wide interface 297 MHz/4 = 74.25 MHz for quad pixel wide interface For more information on how to choose the correct PLL in the targeted devices, see the Video PHY Controller LogiCORE IP Product Guide (PG230) [Ref 22]

Notes:

1. The examples in the Example column are only for reference and do not cover all the possible resolutions. Each GT has its own hardware requirements and limitations. Therefore, to use the HDMI 1.4/2.0 Receiver Subsystem with different GT devices, calculate the clock frequencies and make sure the targeted device is able to support it. When using the HDMI 1.4/2.0 Receiver Subsystem with Xilinx Video PHY Controller IP core, more information can be found in Video PHY Controller LogiCORE IP Product Guide (PG230) [Ref 22].

注释：

1.示例栏中的示例仅供参考，并不涵盖所有可能的解决方案。每个GT都有自己的硬件要求和限制。因此，要将HDMI 1.4/2.0接收机子系统用于不同的GT设备，请计算时钟频率并确保目标设备能够支持它。当使用带有Xilinx视频PHY控制器IP核的HDMI 1.4/2.0接收器子系统时，更多信息可在《视频PHY Controller LogiCORE IP产品指南》（PG230）[参考文献22]中找到。

For example, 1080p60, 12BPC, and 2PPC are used to show how all the clocks are derived.

例如，1080p60、12BPC和2PPC用于显示如何导出所有时钟。

Video Resolution	Horizontal Total	Horizontal Active	Vertical Total	Vertical Active	Frame Rate (Hz)
1080p60	2200	1920	1125	1080	60

Pixel clock represents the total number of pixels need to be sent every second. Therefore,

像素时钟表示每秒需要发送的像素总数。因此

Pixel clock = Htotal × Vtotal × Frame Rate
=2200 x 1125 x 60
=148,500,000
= 148.5Mhz
Link clock = (Data clock)/4=222.75/4=55.6875Mhz
Video clock = (Pixel clock)/PPC=148.5/2=74.25Mhz
Data clock = Pixel clock × BPC/8=148.5× 12/8=222.75Mhz

Using the associative property in this example,

Data clock = 222.75Mhz < 340Mhz
then
TMDS clock = Data clock = 222.75Mhz

P39

Resets

Each AXI input interface has its own reset signal. The reset signals, s_axi_cpu_aresetn, s_axis_video_aresetn and s_axis_audio_aresetn are for S_AXI_CPU_IN, VIDEO_IN (AXI4-Stream Video Interface), and AUDIO_IN respectively. These three reset signals are active-Low. Because the reset signal is used across multiple sub-blocks in the subsystem, keep the system in the reset state until all the clocks are stabilized. You can use the locked signal from the clock generation block as a reset signal.

Note: There is no dedicated hardware reset for VIDEO_OUT interface when Native Video interface is selected. However, HDMI RX Subsystem outputs a video_rst signal, which you can use to reset its supporting Native Video processing modules.

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