赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(11)

2年前更新

读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍此IP的设计步骤。

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Design Flow Steps

This chapter describes customizing and generating the subsystem, constraining the subsystem, and the simulation, synthesis and implementation steps that are specific to this IP subsystem. More detailed information about the standard Vivado® design flows and the IP integrator can be found in the following Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 13]

• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 14]

• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 15]

• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 16]

设计流程步骤

本章描述了定制和生成子系统、约束子系统以及特定于此IP子系统的模拟、合成和实现步骤。有关标准Vivado®设计流程和IP集成商的更多详细信息，请参阅以下Vivado-design Suite用户指南：

•Vivado Design Suite用户指南：使用IP Integrator（UG994）设计IP子系统[参考文献13]

•Vivado Design Suite用户指南：使用IP进行设计（UG896）[参考14]

•Vivado Design Suite用户指南：入门（UG910）[参考文献15]

•Vivado Design Suite用户指南：逻辑模拟（UG900）[参考文献16]

Customizing and Generating the Subsystem

This section includes information about using Xilinx tools to customize and generate the subsystem in the Vivado Design Suite.

The HDMI 1.4/2.0 Receiver Subsystem can be added to a Vivado IP integrator block design in the Vivado Design Suite and can be customized using IP catalog. For more detailed information on customizing and generating the subsystem in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 13]. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl Console.

You can customize the subsystem for use in your design by specifying values for the various parameters associated with the IP subsystem using the following steps:

1. In the Flow Navigator, click on Create Block Diagram or Open Block Design under the

IP Integrator heading.

2. Right click in the diagram and select Add IP.

A searchable IP catalog opens. You can also add IP by clicking on the Add IP button on

the left side of the IP Integrator Block Design canvas.

定制和生成子系统

本节包括有关使用Xilinx工具在Vivado Design Suite中自定义和生成子系统的信息。

HDMI 1.4/2.0接收器子系统可以添加到Vivado design Suite中的Vivado-IP积分器块设计中，并可以使用IP目录进行定制。有关在Vivado IP积分器中定制和生成子系统的更多详细信息，请参阅《Vivado-Design Suite User Guide：Designing IP Subsystems using IP integrator》（UG994）[Ref 13]。IP积分器在验证或生成设计时可能会自动计算某些配置值。要检查值是否更改，请参阅本章中的参数说明。要查看参数值，请在Tcl控制台中运行validate_bd_design命令。

通过使用以下步骤为与IP子系统关联的各种参数指定值，可以自定义设计中使用的子系统：

1.在Flow Navigator中，单击

IP Integrator标题。

2.在图中单击鼠标右键，然后选择“添加IP”。

将打开一个可搜索的IP目录。您还可以通过单击上的add IP（添加IP）按钮添加IP

IP Integrator Block Design画布的左侧。

3. Click on the IP name and press the Enter key on your keyboard or double click on the IP name.

4. Double-click the selected IP block or select the Customize Block command from the right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 14] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 15].

Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE).

The layout depicted here might vary from the current version

3.单击IP名称，然后按键盘上的Enter键或双击IP名称。

4.双击选定的IP块或从右键单击菜单中选择自定义块命令。

有关详细信息，请参阅《Vivado Design Suite用户指南：使用IP进行设计》（UG896）[Ref 14]和《Vivato Design Suite User Guide：入门》（UG190）[参考15]。

注：本章中的数字是Vivado集成设计环境（IDE）的插图。此处描述的布局可能与当前版本不同。

The parameters on the Top level tab are as follows:

Component Name: The component name is set automatically by IP Integrator.

Video Interface: This option selects the Video Interface for the HDMI RX subsystem. The allowable options are AXIS-Stream or Native Video.

Include HDCP 1.4 Decryption: This option enables HDCP 1.4 decryption.

Include HDCP 2.2 Decryption: This option enables HDCP 2.2 decryption.

Max bits per component: This option selects the maximum bits per component. The allowable options are, 8, 10, 12 or 16 bits. This parameter is to set the maximum “allowed” bits per component, and the actual bits per component can be set from the software API to a different value. However, the actual bits per component is bounded by the Max bits per component. For example, if the Max bits per component is set to 16, the user can set the actual bits per component from the software API to any of the values, 8, 10, 12 or 16. But if the Max bits per component is set to 8, you can only set the actual bits per component to 8 through the software API.

Number of pixels per clock on Video Interface: This option selects the number of pixels per clock. The allowable options are 2 or 4 pixels.

IMPORTANT: Pixels per clock (PPC) can only be selected at IP generation time, and must remain static in the design. Some video format with a total horizontal resolution that is NOT divisible by 4 (for example, 720p60 has a total horizontal pixel of 1650, which is not divisible by 4) are not supported. If the design is intended to support this kind of video formats, ensure that PPC=2 is selected in Vivado.

顶层选项卡上的参数如下：

组件名称：组件名称由IP Integrator自动设置。

视频接口：此选项选择HDMI RX子系统的视频接口。允许的选项是AXIS流或本地视频。

Include HDCP 1.4 Decryption：此选项启用HDCP 1.4解密。

Include HDCP 2.2 Decryption：此选项启用HDCP 2.2解密。

每个组件的最大位数：此选项选择每个组件的最高位数。允许的选项为8、10、12或16位。此参数用于设置每个组件的最大“允许”位，每个组件的实际位可以从软件API设置为不同的值。但是，每个组件的实际位数受每个组件的最大位数限制。例如，如果每个组件的最大位数设置为16，则用户可以将软件API中每个组件的实际位数设置为任何值8、10、12或16。但是，如果每个部件的最大位数设为8，则只能通过软件API将每个组件的实际位数设置为8。