赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(13)

读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍此IP的用户参数。

P45

User Parameters

Table 4-1 shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).

用户参数

表4-1显示了Vivado IDE中的字段与用户参数（可在Tcl控制台中查看）之间的关系。

Table 4‐1: Vivado IDE Parameter to User Parameter Relationship

Table 4‐1: Vivado IDE Parameter to User Parameter Relationship (Cont’d)

Output Generation

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 14].

输出生成

有关详细信息，请参阅《Vivado Design Suite用户指南：使用IP进行设计》（UG896）[参考文献14]。

Constraining the Subsystem

This section contains information about constraining the subsystem in the Vivado Design Suite.

Required Constraints

There are clock frequency constraints for the s_axi_cpu_aclk, s_axis_video_aclk,s_axis_audio_aclk, link_clk, and video_clk. For example,

create_clock -name s_axi_cpu_aclk -period 10.0 [get_ports s_axi_cpu_aclk]

create_clock -name s_axis_audio_aclk -period 10.0 [get_ports s_axis_audio_aclk]

create_clock -name link_clk -period 13.468 [get_ports link_clk]

create_clock -name video_clk -period 6.734 [get_ports video_clk]

create_clock -name s_axis_video_aclk -period 5.0 [get_ports s_axis_video_aclk]

When using this subsystem in the Vivado® Design Suite flow with Video PHY Controller modules, link_clk and video_clk are generated from the Video PHY Controller. Therefore, the clock constraints are set to the Video PHY Controller constraints instead of these generated clocks. See Clocking in the Video PHY Controller LogiCORE™ IP Product Guide (PG230) [Ref 22] for more information.

s_axi_cpu_aclk, s_axis_video_aclk, and s_axis_audio_aclk constraints are generated at system-level, for example by using a clock wizard.

在Vivado®Design Suite流中使用此子系统与Video PHY控制器模块时，link_clk和Video_clk是从Video PHY控制器生成的。因此，时钟约束被设置为视频PHY控制器约束，而不是这些生成的时钟。请参阅视频PHY控制器LogiCORE中的时钟™ IP产品指南（PG230）[参考文献22]了解更多信息。

例如，通过使用时钟向导，可以在系统级别生成s_axi_cpu_aclk、s_axis_video_aclk和s_axis_audio_aclk约束。

Device, Package, and Speed Grade Selections

For more information on the device constraint/dependency, see the Video PHY Controller LogiCORE IP Product Guide (PG230) [Ref 22].

Table 4-2 shows the device and speed grade selections for HDMI 1.4/2.0 Receiver Subsystem.

设备、包装和速度等级选择

有关设备约束/依赖性的更多信息，请参阅Video PHY Controller LogiCORE IP Product Guide（PG230）[Ref 22]。

表4-2显示了HDMI 1.4/2.0接收机子系统的设备和速度等级选择。

Table 4‐2: Device and Speed Grade Selections

Notes:
1. All HDMI 1.4 resolutions can be supported.
2. Full HDMI 2.0 resolutions support up to 4096 x 2160 @ 60fps.

注释：

1.支持所有HDMI 1.4分辨率。

2.全HDMI 2.0分辨率最高支持4096 x 2160@60fps。

Clock Frequencies

The AXI4-Lite CPU clock must run at 100 Mhz. See Clocking in Chapter 3 for more information.

时钟频率

AXI4 Lite CPU时钟必须以100 Mhz的频率运行。请参阅第3章中的Clocking更多信息。

Clock Management

This section is not applicable for this IP subsystem.

时钟管理

本节不适用于此IP子系统。

Clock Placement

This section is not applicable for this IP subsystem.

时钟布局

本节不适用于此IP子系统。