赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(12)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(12)

读赛灵思IP手册,HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide,即HDMI接受器系统的手册。本期介绍此IP的配置界面。

 

P43

Video Bridge Tab (Video AXI4 Stream Interface Only)

The Video Bridge tab is shown in Figure 4-2.

视频网桥选项卡(仅限视频AXI4流接口)

视频桥选项卡如图4-2所示。

图片[1]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(12)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

 

The parameter on the Video Bridge tab is as follows:

FIFO Depth: Specifies the number of locations in the input FIFO. The allowable values are 32, 1024, 2048, 4096, and 8192.

视频桥选项卡上的参数如下:

FIFO深度:指定输入FIFO中的位置数。允许值为321024204840968192

Native Video Interface Option

The native video interface option window is shown in Figure 4-3

本机视频接口选项

本地视频界面选项窗口如图4-3所示

图片[2]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(12)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

 

Include HDCP 1.4 Decryption: This option enables HDCP 1.4 decryption.

Include HDCP 2.2 Decryption: This option enables HDCP 2.2 decryption.

Note: HDCP 1.4 and 2.2 Decryption options are only configurable if you have a HDCP license, else it is disabled.

Include HDCP 1.4 Decryption:此选项启用HDCP 1.4解密。

Include HDCP 2.2 Decryption:此选项启用HDCP 2.2解密。

注意:HDCP 1.42.2解密选项仅在您拥有HDCP许可证时才可配置,否则将被禁用。

The Top level tab without a valid HDCP license is shown in Figure 4-4.

没有有效HDCP许可证的顶层选项卡如图4-4所示。

图片[3]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(12)-Xilinx-AMD社区-FPGA CPLD-ChipDebug

 

 

 

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