读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍此IP的设计示例。
Example Design
This chapter contains step-by-step instructions for generating an HDMI Example Design from the HDMI 1.4/2.0 Receiver Subsystem by using Vivado® Flow.
设计示例
本章包含使用Vivado®Flow从HDMI 1.4/2.0接收器子系统生成HDMI示例设计的逐步说明。
Running the Example Design
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1. Open the Vivado Design Suite and create a new project.
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2. In the pop-up window, press Next 5 times.
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3. Select the Board. (KC705, ZC706, and KCU105 are supported.)
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4. Click Finish.
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5. Click IP Catalog and select HDMI 1.4/2.0 Receiver Subsystem under Video Connectivity, then double click on it.
运行示例设计
1.打开Vivado Design Suite并创建新项目。
2.在弹出窗口中，按“下一步”5次。
3.选择电路板。（支持KC705、ZC706和KCU105。）
4.单击“完成”。
5.单击IP Catalog（IP目录），然后在Video Connectivity（视频连接）下选择HDMI 1.4/2.0 Receiver Subsystem（HDMI 1.4/20接收器子系统），然后双击它。
![图片[1]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/21671683038.png)
° For the Example Design flow, Native Video Interface is not supported.
° You can rename the IP component name, which is used as example design project name.
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1. Configure HDMI 1.4/2.0 Receiver Subsystem, then click OK.
°对于Example Design流程，不支持Native Video Interface。
°您可以重命名IP组件名称，该名称用作示例设计项目名称。
6.配置HDMI 1.4/2.0接收器子系统，然后单击确定。
![图片[2]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/91671683042.png)
The Generate Output Products dialog box appears.
此时会出现生成输出产品对话框。
7. Click on Generate.
a. You may optionally click Skip if you just want to generate the example design
7.单击生成。
a、 如果只想生成示例设计，可以选择单击“跳过”
![图片[3]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/51671683052.png)
8. Right click on the HDMI 1.4/2.0 Receiver Subsystem component under Design source,
and click Open IP Example Design.
8.右键单击Design source下的HDMI 1.4/2.0 Receiver Subsystem组件，
然后单击打开IP示例设计。
![图片[4]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/91671683053.png)
9. Choose the target project location, then click OK.
9.选择目标项目位置，然后单击“确定”。
![图片[5]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/01671683053.png)
The IPI Design is then generated. You may choose to Run Synthesis, Implementation, or Generate Bitstream. 然后生成IPI设计。您可以选择运行合成、实现或生成比特流。
![图片[6]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/31671683055.png)
An overall system IPI block diagram of the KC705 based example design is shown below
基于KC705的示例设计的总体系统IPI框图如下所示
![图片[7]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/11671683055.png)
10. Export Hardware to prepare for SDK Example Design Flow
10.导出硬件以准备SDK示例设计流
![图片[8]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/31671683056.png)
P59
11. Click OK. (Use the default Export Location <Local to Project> for the example design.)
12. Launch SDK.
11.单击“确定”。（对于示例设计，使用默认的导出位置<本地到项目>。）
12.启动SDK。
![图片[9]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/01671683057.png)
13. Choose SDK workspace location. By default, it is “Local to Project.
13.选择SDK工作区位置。默认情况下，它是“本地到项目”。
![图片[10]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/81671683057.png)
Vivado SDK is launched. Vivado SDK打开。
![图片[11]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/71671683058.png)
14. Create Board Support Package. 14.创建板级支持包
![图片[12]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/91671683059.png)
15. Enter BSP project name and click Finish
15.输入BSP项目名称，然后单击“完成”
![图片[13]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/21671683060.png)
16. Click OK
17. Find the HDMI 1.4/2.0 Receiver Subsystem and click on Import Examples.
16.单击“确定”
17.找到HDMI 1.4/2.0接收器子系统，然后单击导入示例。
![图片[14]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/31671683061.png)
18. Select xhdmi_example.
For project generated for KC705 and KCU105 boards (MicroBlaze™ soft processor core based), select xhdmi_example.
For project generated for ZC706 boards (Zynq®-7000 SoC ARM processor based), select xhdmi_example_zynq.
18.选择xhdmi_example。
用于为KC705和KCU105板（MicroBlaze）生成的项目™基于软处理器内核），选择xhdmi_example。
对于为ZC706板（基于Zynq®-7000 SoC ARM处理器）生成的项目，选择xhdmi_example_Zynq。
![图片[15]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/01671683061.png)
The example application is built successfully. The .elf is ready to use.
示例应用程序已成功构建。.elf已准备好使用。
![图片[16]-赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(14)-Xilinx-AMD社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2022/12/81671683062.png)
P65 Running the Reference Design (KC705)
Use the following steps to execute the system using generated bitstream and software elf from the example design
1. Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx Design Tools > Vivado 2017.1 > Vivado 2017.1 Tcl Shell.
2. In the Xilinx command shell window, change to the Example Design Project directory:
Vivado% cd ./v_hdmi_rx_ss_0_ex
3. Invoke Xilinx System Debugger (xsdb).
Vivado% xsdb
4. Establish connections to debug targets.
xsdb% connect
5. Download the bitstream to the FPGA.:
xsdb% fpga -file ./v_hdmi_rx_ss_0_ex.runs/impl_1/exdes_wrapper.bit
6. Set the target processor.
xsdb% target -set 3
7. Download the software .elf to the FPGA.
xsdb% dow ./v_hdmi_rx_ss_0_ex.sdk/<name of bsp>_xhdmi_example_1/
Debug/<name of bsp>_xhdmi_example_1.elf
8. Run the software.
xsdb% stop
xsdb% rst
xsdb% con
9. Exit the XSDB command prompt.
xsdb% exit
IMPORTANT: When using the TB-FMCH-HDMI4K example design with the KCU105 board, you must set the FMC VADJ_1V8 Power Rail before programing the FPGA with bitstream generated from Example Design Flow. KCU105 Board FMCH VADJ Adjustment shows the steps on how to set the VADJ power rail when using KCU105 board. For more details about KCU105 Board, to KCU105 Board User Guide [Ref 18]
运行参考设计（KC705）
使用示例设计中生成的比特流和软件elf，使用以下步骤执行系统
1.选择“开始”>“所有程序”>“Xilinx Design Tools”>“Vivado 2017.1”>“Vivado 2017 Tcl Shell”，启动Xilinx System Debugger。
2.在Xilinx命令shell窗口中，切换到Example Design Project目录：
Vivado% cd ./v_hdmi_rx_ss_0_ex
3.调用Xilinx系统调试器（xsdb）。
Vivado %xsdb
4.建立与调试目标的连接。
xsdb% connect
5.将比特流下载到FPGA
xsdb% fpga -file ./v_hdmi_rx_ss_0_ex.runs/impl_1/exdes_wrapper.bit
6.设置目标处理器。
xsdb% target -set 3
7.将软件.elf下载到FPGA。
xsdb% dow ./v_hdmi_rx_ss_0_ex.sdk/<name of bsp>_xhdmi_example_1/
Debug/<name of bsp>_xhdmi_example_1.elf
8.运行软件。
xsdb% stop
xsdb% rst
xsdb% con
9.退出XSDB命令提示符。
xsdb% exit
重要提示：在KCU105板上使用TB-FMCH-HDMI4K示例设计时，必须先设置FMC VADJ_1V8 Power Rail，然后才能使用示例设计流生成的比特流对FPGA进行编程。KCU105板FMCH VADJ调整显示了使用KCU105板卡时如何设置VADJ电源轨的步骤。有关KCU105板的更多详细信息，请参阅KCU105板卡用户指南[参考18]
