赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(16)

读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍附录A验证、法规遵从性和互操作性。

 

 

P67

Appendix A

Verification, Compliance, and Interoperability

附录A

验证、法规遵从性和互操作性

Interoperability

Interoperability tests for the HDMI 1.4/2.0 Receiver Subsystem have been conducted with the following hardware setup.

互操作性

HDMI 1.4/2.0接收机子系统的互操作性测试已通过以下硬件设置进行。

Hardware Testing

The HDMI 1.4/2.0 Receiver Subsystem has been validated using

• Kintex®-7 FPGA Evaluation Kit (KC705)

• Kintex® UltraScale™ FPGA Evaluation Kit (KCU105)

• Inrevium Artix-7 FPGA ACDC A7 Evaluation Board

• Zynq®-7000 All Programmable SoC evaluation board (ZC706)

硬件测试

HDMI 1.4/2.0接收机子系统已使用

•Kintex®-7 FPGA评估套件（KC705）

•Kintex®UltraScale™ FPGA评估套件（KCU105）

•Inrevium Artix-7 FPGA ACDC A7评估委员会

•Zynq®-7000全可编程SoC评估板（ZC706）

This release is tested with the following source devices:

此版本通过以下源设备进行测试：

• Quantum Data 980B

• Quantum Data 780B

• Apple TV (Gen 2/3/4)

• Android M8 media player

• Apple MacBook Pro

• Google Chromecast

• Open Hour media box

• Dell Latitude laptop (E7240)

• Intel HD Graphics 4000

• Nvidia GTX970 graphics card

• UGOOS media box

• LG 27mu67

• LG BP736

• Philips BDP2180K

• Sony BDP-S3500

• Sony BDP-S6500

• Samsung BD-J5900

• Murideo video generator / SIX-G

•Nvidia shield

• Roku 4

• Nvidia GTX980

Video Resolutions

Figure A-1 shows the hardware setup for AXI4-Stream Video Interface. An HDMI source connects to Video PHY Controller, which converts the HDMI Video into LINK DATA and sends to the HDMI RX Subsystem. Then, the HDMI RX Subsystem translates the LINK DATA into AXI4-Stream Video and sends to the Test Pattern Generator. By setting the Test Pattern Generator to pass-through mode, the AXI4-Stream Video from the HDMI RX Subsystem is passed to HDMI TX Subsystem where it gets translated to LINK DATA again and sends back to the Video PHY Controller. The Video PHY Controller then converts it back to HDMI Video and sends to HDMI Sink.

视频解决方案

图A-1显示AXI4流视频接口的硬件设置。HDMI源连接到视频PHY控制器，该控制器将HDMI视频转换为链接数据，并发送到HDMI RX子系统。然后，HDMI RX子系统将链接数据转换为AXI4流视频并发送到测试模式生成器。通过将测试模式生成器设置为直通模式，来自HDMI RX子系统的AXI4流视频被传递到HDMI TX子系统，在那里它再次转换为LINK DATA并发送回视频PHY控制器。视频PHY控制器然后将其转换回HDMI视频并发送到HDMI接收器。

For Video PHY Controller settings and PLL selections, see the Video PHY Controller LogiCORE IP Product Guide (PG230) [Ref 22].

Similarly, Figure A-2 shows the hardware setup for Native Video Interface. The only difference is that two Video Bridge modules are added in between the HDMI RX Subsystem and the Test Pattern Generator, and between the Test Pattern Generator to the HDMI TX Subsystem.

有关Video PHY Controller设置和PLL选择，请参阅Video PHY Controller LogiCORE IP Product Guide（PG230）[Ref 22]。

同样，图A-2显示了本机视频接口的硬件设置。唯一的区别是在HDMI RX子系统和测试模式生成器之间，以及在测试模式生成器和HDMI TX子系统之间添加了两个视频桥模块。

Table A-1, Table A-2, and Table A-3 show the video resolutions that were tested as part of the release for different video formats.

表A-1、表A-2和表A-3显示了作为不同视频格式发布的一部分而测试的视频分辨率。

Table A‐1: Tested Video Resolutions for RGB 4:4:4 and YCbCr 4:4:4

Resolution	Horizontal		Vertical		Frame Rate (Hz)
	Total	Active	Total	Active
480i60	858	720	525	480	60
1080i50	2640	1920	1125	1080	50
1080i60	2200	1920	1125	1080	60
480p60	858	720	525	480	60
576p50	864	720	625	576	50
720p50	1980	1280	750	720	50
720p60	1650	1280	750	720	60
1080p24	2750	1920	1125	1080	24
1080p25	2640	1920	1125	1080	25
1080p30	2200	1920	1125	1080	30
1080p50	2640	1920	1125	1080	50
1080p60	2200	1920	1125	1080	60
1080p120	2200	1920	1125	1080	120
2160p24	5500	3840	2250	2160	24
2160p25	5280	3840	2250	2160	25
2160p30	4400	3840	2250	2160	30
2160p60	4400	3840	2250	2160	60
096x2160p60	4400	4096	2250	2160	60
vgap60	800	640	525	480	60
svgap60	1056	800	628	600	60
xgap60	1344	1024	806	768	60
sxgap60	1688	1280	1066	1024	60
wxgap60	1440	1280	790	768	60
wxga+p60	1792	1366	798	768	60
uxgap60	2160	1600	1250	1200	60
wuxgap60	2592	1920	1245	1200	60
wsxgap60	2240	1680	1089	1050	60

 

 

 

Notes:

1. Not all resolutions can be supported due to VPHY limitation. For details, refer to Video PHY Controller LogiCORE IP Product Guide (PG230) [Ref 22].

2. In this release, UXGA 60 Hz is supported in the HDMI 1.4/2.0 Receiver Subsystem for 8, 10, and 12 bits per component only.

注释：

1.由于VPHY限制，并非所有分辨率都可以支持。有关详细信息，请参阅Video PHY Controller LogiCORE IP Product Guide（PG230）[Ref 22]。

2.在此版本中，HDMI 1.4/2.0接收器子系统仅支持每个组件8、10和12位的UXGA 60 Hz。

Table A‐2: Tested Video Resolutions for YCbCr 4:2:2 at 12 Bits/component

 

Resolution	Horizontal		Vertical		Frame Rate (Hz)
	Total	Active	Total	Active
1080i50	2640	1920	1125	1080	50
1080i60	2200	1920	1125	1080	60
480p60	858	720	525	480	60
576p50	864	720	625	576	50
720p50	1980	1280	750	720	50
720p60	1650	1280	750	720	60
1080p24	2750	1920	1125	1080	24
1080p25	2640	1920	1125	1080	25
1080p30	2200	1920	1125	1080	30
1080p50	2640	1920	1125	1080	50
1080p60	2200	1920	1125	1080	60
2160p24	5500	3840	2250	2160	24
2160p25	5280	3840	2250	2160	25
2160p30	4400	3840	2250	2160	30
vgap60	800	640	525	480	60
svgap60	1056	800	628	600	60
wxgap60	1440	1280	790	768	60
wxga+p60	1792	1366	798	768	60
uxgap60	2160	1600	1250	1200	60
wuxgap60	2592	1920	1245	1200	60
wsxgap60	2240	1680	1089	1050	60

 

Table A‐3: Tested Video Resolutions for YCbCr 4:2:0 at 8, 10, 12, 16 Bits/Component

Resolution	Horizontal		Vertical		Frame Rate (Hz)
	Total	Active	Total	Active	1
2160p60	4400	3840	2250	2160	60