读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍附录B调试。
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Appendix B
Debugging
This appendix includes details about resources available on the Xilinx Support website and debugging tools.
TIP: If the IP generation halts with an error, there might be a license issue. See License Checkers in Chapter 1 for more details.
附录B
调试
本附录包括有关Xilinx支持网站上可用资源和调试工具的详细信息。
提示：如果IP生成因错误而停止，则可能存在许可证问题。有关更多详细信息，请参阅第1章中的许可证检查器。
Finding Help on Xilinx.com
To help in the design and debug process when using the HDMI 1.4/2.0 Receiver Subsystem, the Xilinx Support web page contains key resources such as product documentation, release notes, answer records, information about known issues, and links for obtaining further product support.
在Xilinx.com上查找帮助
为了在使用HDMI 1.4/2.0接收器子系统时帮助设计和调试过程，Xilinx支持网页包含关键资源，如产品文档、发行说明、答案记录、已知问题的信息以及获取进一步产品支持的链接。
Documentation
This product guide is the main document associated with the HDMI 1.4/2.0 Receiver Subsystem. This guide, along with documentation related to all products that aid in the design process, can be found on the Xilinx Support web page or by using the Xilinx Documentation Navigator.
文档
本产品指南是与HDMI 1.4/2.0接收机子系统相关的主要文档。本指南以及与所有有助于设计过程的产品相关的文档，可以在Xilinx支持网页上或使用XilinxDocumentationNavigator找到。
Download the Xilinx Documentation Navigator from the Downloads page. For more information about this tool and the features available, open the online help after installation.
从下载页面下载Xilinx文档导航器。有关此工具和可用功能的详细信息，请在安装后打开联机帮助。
Answer Records
Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.
应答记录
答案记录包括关于常见问题的信息、关于如何解决这些问题的有用信息以及关于Xilinx产品的任何已知问题。每天都会创建和维护答案记录，以确保用户能够访问最准确的可用信息。
Answer Records for this subsystem can be located by using the Search Support box on the main Xilinx support web page. To maximize your search results, use proper keywords such as
• Product name
• Tool message(s)
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
Master Answer Record for the HDMI 1.4/2.0 Receiver Subsystem
AR: 54546
使用Xilinx支持主页上的搜索支持框可以找到此子系统的应答记录。要最大化搜索结果，请使用适当的关键字，例如
•产品名称
•工具消息
•所遇到问题的总结
返回结果后，可以进行筛选搜索，以进一步确定结果的目标。
HDMI 1.4/2.0接收机子系统的主应答记录
注册号：54546
Technical Support
Xilinx provides technical support at the Xilinx Support web page for this LogiCORE™ IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
To contact Xilinx Technical Support, navigate to the Xilinx Support web page.
技术支持
Xilinx在Xilinx支持网页上为此LogiCORE提供技术支持™ 如产品文档中所述使用IP产品。如果您执行以下任一操作，Xilinx无法保证时间、功能或支持：
•在文档中未定义的设备中实施解决方案。
•定制超出产品文档允许范围的解决方案。
•更改设计中标有“请勿修改”的任何部分。
要联系Xilinx技术支持，请导航到Xilinx支持网页。
Debug Tools
Tools are available to address HDMI 1.4/2.0 Receiver Subsystem design issues. It is important to know which tools are useful for debugging various situations.
调试工具
有工具可用于解决HDMI 1.4/2.0接收机子系统设计问题。了解哪些工具对调试各种情况有用是很重要的。
Vivado Design Suite Debug Feature
The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into your design. The debug feature also allows you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx devices.
The Vivado logic analyzer is used with the logic debug IP cores, including:
• ILA 2.0 (and later versions)
• VIO 2.0 (and later versions)
Vivado Design Suite调试功能
Vivado®Design Suite调试功能将逻辑分析仪和虚拟I/O内核直接插入到您的设计中。调试功能还允许您设置触发条件，以捕获硬件中的应用程序和集成块端口信号。然后可以分析捕获的信号。Vivado IDE中的此功能用于在Xilinx设备中运行的设计的逻辑调试和验证。
Vivado逻辑分析仪与逻辑调试IP核一起使用，包括：
•ILA 2.0（及更高版本）
•VIO 2.0（及更高版本）
See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 19].
参见《Vivado Design Suite用户指南：编程和调试》（UG908）[参考文献19]。
Reference Boards
Various Xilinx development boards support the HDMI 1.4/2.0 Receiver Subsystem. These boards can be used to prototype designs and establish that the subsystem can communicate with the system.
• 7 series FPGA evaluation board
° KC705
• UltraScale FPGA evaluation board
° KCU105
• Zynq-7000 All Programmable SoC evaluation board
° ZC706
参考委员会
各板卡种Xilinx开发板支持HDMI 1.4/2.0接收器子系统。这些板可用于原型设计，并确定子系统可以与系统通信。
•7系列FPGA评估板
°KC705
•UltraScale FPGA评估板
°KCU105
•Zynq-7000全可编程SoC评估板
°ZC706
Hardware Debug
Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The Vivado debug feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the debug feature for debugging the specific problems.
硬件调试
硬件问题可以从链接问题到数小时测试后发现的问题。本节提供常见问题的调试步骤。Vivado调试功能是硬件调试中使用的宝贵资源。以下各节中提到的信号名称可以使用调试功能进行探测，以调试特定问题。
General Checks
• Ensure that all the timing constraints and all other constraints were met during implementation.
• Ensure that all clock sources are active and clean.
• If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.
• If your outputs go to 0, check your licensing.
° User LEDs (KC705/KCU105/ZC706)
° LED0 – HDMI TX subsystem lock (when HDMI Example Design is used)
一般检查
•确保在实施过程中满足所有时间限制和所有其他限制。
•确保所有时钟源处于活动状态且干净。
•如果在设计中使用MMCM，请确保所有MMCM都已通过监控锁定端口获得锁定。
•如果输出为0，请检查您的许可证。
°用户LED（KC705/KCU105/ZC706）
°LED0-HDMI TX子系统锁定（使用HDMI示例设计时）
Interface Debug
AXI4-Lite Interfaces
Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:
• The s_axi_aclk and aclk inputs are connected and toggling.
• The interface is not being held in reset, and s_axi_areset is an active-Low reset.
• The interface is enabled, and s_axi_aclken is active-High (if used).
• The main subsystem clocks are toggling and that the enables are also asserted.
AXI4-Stream Interfaces
If data is not being transmitted or received, check the following conditions:
• If transmit <interface_name>_tready is stuck Low following the
<interface_name>_tvalid input being asserted, the subsystem cannot send data.
• If the receive <interface_name>_tvalid is stuck Low, the subsystem is not receiving data.
• Check that the aclk inputs are connected and toggling.
• Check that the AXI4-Stream waveforms are being followed.
• Check subsystem configuration.
接口调试
AXI4 Lite接口
从没有将所有0作为默认值的寄存器中读取，以验证接口是否正常工作。当读取地址有效时，Output s_axi_arready断言，当读取数据/响应有效时，输出s_axi_ravalid断言。如果接口无响应，请确保满足以下条件：
•s_axi_aclk和aclk输入连接并切换。
•接口未保持重置状态，且s_axi_areset为激活的低重置。
•接口已启用，且s_axi_aclken处于高激活状态（如果使用）。
•主子系统时钟正在切换，启用也被断言。
AXI4流接口
如果未发送或接收数据，请检查以下情况：
•如果传输<interface_name>_tready在
<interface_name>_tvalid输入被断言，子系统无法发送数据。
•如果receive<interface_name>_tvalid一直处于低位，则子系统未接收数据。
•检查aclk输入是否连接并切换。
•检查是否遵循AXI4流波形。
•检查子系统配置。
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