ZYNQ-延迟打拍-Xilinx-AMD论坛-FPGA CPLD-ChipDebug

ZYNQ-延迟打拍

//对图像矩阵数据的计算共耗时5个周期,
//所以要将控制信号延时5个周期
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        matrix_frame_vsync_dly <= 0;
        matrix_frame_href_dly  <= 0;
        matrix_frame_clken_dly <= 0;
    end
    else begin
        matrix_frame_vsync_dly <= { matrix_frame_vsync_dly[3:0] , matrix_frame_vsync };
        matrix_frame_href_dly  <= { matrix_frame_href_dly[3:0]  , matrix_frame_href  };
        matrix_frame_clken_dly <= { matrix_frame_clken_dly[3:0] , matrix_frame_clken };
    end
end

 

 

结论:
1:每一次非阻塞赋值(<=)都需要一个时钟上升沿clk才能完成
2:{ matrix_frame_clken_dly[3:0] , matrix_frame_clken };逻辑运算不消耗c时间,当作瞬间完成
3:

matrix_frame_vsync_dly <= { matrix_frame_vsync_dly[3:0] , matrix_frame_vsync };
matrix_frame_vsync_dly <= matrix_frame_vsync_dly【0】
matrix_frame_vsync_dly <= matrix_frame_vsync_dly【1】
matrix_frame_vsync_dly <= matrix_frame_vsync_dly【2】
matrix_frame_vsync_dly <= matrix_frame_vsync_dly【3】
matrix_frame_vsync_dly <= matrix_frame_vsync_dly【4】

总共经过5歌clk,延迟打5拍

 

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