xpm fifo的empty一直为1怎么解决

使用了xpm的同步fifo，almost_empty已经在写入后由1变为0，但empty没有，直接用ip核也可以正常，是哪里出错了

仿真和代码：

module fifo_tb(

    );
    
    reg clk;
    reg rst;
    reg [31:0]din;
    reg rd_en;
    reg wr_en;
    wire [31:0]dout;
    wire almost_empty;
    wire almost_full;
    wire valid;
    wire full;
    wire empty;
    wire wr_ack;
    wire underflow;
    wire overflow;
    
   xpm_fifo_sync #(
       .CASCADE_HEIGHT(0),        // DECIMAL
       .DOUT_RESET_VALUE("0"),    // String
       .ECC_MODE("no_ecc"),       // String
       .FIFO_MEMORY_TYPE("auto"), // String
       .FIFO_READ_LATENCY(1),     // DECIMAL
       .FIFO_WRITE_DEPTH(32),   // DECIMAL
       .FULL_RESET_VALUE(0),      // DECIMAL
       .PROG_EMPTY_THRESH(10),    // DECIMAL
       .PROG_FULL_THRESH(10),     // DECIMAL
       .RD_DATA_COUNT_WIDTH(5),   // DECIMAL
       .READ_DATA_WIDTH(32),      // DECIMAL
       .READ_MODE("std"),         // String
       .SIM_ASSERT_CHK(1),        // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
       .USE_ADV_FEATURES("1f1f"), // String
       .WAKEUP_TIME(0),           // DECIMAL
       .WRITE_DATA_WIDTH(32),     // DECIMAL
       .WR_DATA_COUNT_WIDTH(5)    // DECIMAL
    )
    xpm_fifo_sync_inst (
        .almost_empty(almost_empty), 
        .almost_full(almost_full),
        .data_valid(valid),
        .dbiterr(), 
        .dout(dout),
        .empty(empty),  
        .full(full), 
        .overflow(overflow), 
        .prog_empty(),
        .prog_full(),
        .rd_data_count(),
        .rd_rst_busy(),
        .sbiterr(),
        .underflow(underflow),
        .wr_ack(wr_ack),
        .wr_data_count(),
        .wr_rst_busy(),
        .din(din),
        .injectdbiterr(0),
        .injectsbiterr(0),
        .rd_en(rd_en),
        .rst(rst), 
        .sleep(0),
        .wr_clk(clk), 
        .wr_en(wr_en)
     );
   
    always #1 clk = ~clk;
    
    integer i;
    
    initial begin
        i=0;
        clk=1;
        rst=1;
        rd_en=0;
        wr_en=0;
        din=0;
        #250
        rd_en=0;
        wr_en=0;
        rst=0;
        #250
        for(i=0;i<=32;i=i+1)begin
            #2
            din=i;
            wr_en=1;
        end
        #2
        wr_en=0;
        #10
        rd_en=1;
        #32
        rd_en=0;              
    end
    
endmodule