【提问】请问提示 HDL-8007 ERROR: cc is a black box in cc.v(1)怎么解决-Anlogic-安路社区-FPGA CPLD-ChipDebug

已解决请问提示 HDL-8007 ERROR: cc is a black box in cc.v(1)怎么解决

文件名也是对的

module cc(

input wire clk, // 系统时钟信号

input reg !rst, // 复位信号

input wire key, // 按键信号

input wire [11:0] Iin_w //12位ADC输入

output wire pwm_out_s // PWM 输出

output wire Ns

output wire Rf

);

// 按键消抖计数器参数

parameter DEBOUNCE_COUNT = 10000; // 调整消抖时间

reg D_r_1;

reg D_r_2;

reg D_f_1;

reg D_f_2;

reg [11:0] debounce; // 按键消抖计数器

reg [11:0] counter; // 计数器,用于生成延时

reg pwm_state; // PWM 状态,1 表示 70% 占空比,0 表示 50% 占空比

reg c1; //上升过程比较器判断

reg c2; //下降过程比较器判断

reg [11:0] pwm_count; // PWM 计数器

reg [11:0] Iin;

reg Ns_d;

reg Rff_d;

assign clk_r_1 = pwm_state;//上升沿触发

assign clk_r_2 = Ns_d&c1; //上升沿触发

assign clk_f_1 = ~pwm_state;//上升沿触发

assign clk_f_2 = Rff_d&c2;

assign Ns = D_r_1^D_r_2;

assign Rff = D_f_1^D_f_2;

assign Rf = ~Rff;

assign S = ~(Ns|Rff);

assign pwm_out_s = ((pwm_count < (pwm_state ? 4200 : 3000)) ? 1'b1 : 1'b0)&S;

always@(posedge clk or negedge rst)begin

if(!rst) begin

end else begin

Ns_d <= Ns;

Rff_d <= Rff;

end

end

always@(posedge clk_r_1 or negedge rst) begin

if(!rst) begin

D_r_1=0;

end else begin

D_r_1 <= ~D_r_1;

end

end

always@(posedge clk_r_2 or negedge rst) begin

if(!rst) begin

D_r_2=0;

end else begin

D_r_2 <= ~D_2_1;

end

end

always@(posedge clk_f_1 or negedge rst) begin

if(!rst) begin

D_f_1=0;

end else begin

D_f_1 <= ~D_f_1;

end

end

always@(posedge clk_f_2 or negedge rst) begin

if(!rst) begin

D_f_2=0;

end else begin

D_f_2 <= ~D_f_2;

end

end

always@(posedge clk or negedge rst) begin

if(!rst) begin

Iin <= 0;

end else begin

Iin <= Iin_w;

end

if(Iin > 12'h7FF )begin

c1 <= 1;

end else begin

c1 <= 0;

end

if(Iin < 12'h400 )begin

c2 <= 1;

end else begin

c2 <= 0;

end

end

always @(posedge clk or negedge rst) begin

if (!rst) begin

debounce <= 0;

counter <= 0;

pwm_count <= 0;

pwm_state <= 0;

end else begin

// 按键消抖

if (key) begin

if (debounce < DEBOUNCE_COUNT)

debounce <= debounce + 1;

end else begin

debounce <= 0;

end

// 生成延时

if (counter < 200000) // 200ms 延时,根据时钟频率调整

counter <= counter + 1;

else

counter <= 0;

// 生成 PWM 波

if (pwm_count < 6000) // 调整 PWM 周期,根据时钟频率调整

pwm_count <= pwm_count + 1;

else

pwm_count <= 0;

if (debounce == DEBOUNCE_COUNT)

pwm_state <= 1;

else if (counter == 0)

pwm_state <= 0;

end

end

endmodule

 

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