Error: Can’t communicate with the CPU-易灵思(Elitestek)论坛-FPGA CPLD-ChipDebug

Error: Can’t communicate with the CPU

RISCV debug报错

Open On-Chip Debugger 0.11.0+dev-04034-gfaf2fc486-dirty (2023-05-02-16:04)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
D:\Onboard_tranning\DDR3_Controller_V17_ti60_soc_v1\par\ddr_demo_ti60\embedded_sw\sapphire_soc
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : set servers polling period to 50ms
Info : clock speed 800 kHz
Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x10660a79 (mfg: 0x53c (Efinix Inc), part: 0x0660, ver: 0x1)
Error: fpga_spinal.bridge: IR capture error; saw 0x05 not 0x01
Warn : Bypassing JTAG setup events due to errors
Error: !!!
Error: Can't communicate with the CPU
Error: !!!
Warn : target fpga_spinal.cpu0 examination failed
Info : starting gdb server for fpga_spinal.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet

 

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