[VA INTERNAL ERROR-1000]XL_易灵思FPGA7个月前发布90[VA INTERNAL ERROR-1000] FILE C:/swtools/MinGW/msys/1.0/home/jenkins/workspace/BuildEfinity/rushc/customer/Efinix/src/util/EfxUtil.cpp at line 1162 0 != outNet “” 错误原因：信号的输入输出方向定义反了。在应用中把输出定义成了输入 input wire dout_ready,
![[VA INTERNAL ERROR-1000]-易灵思(Elitestek)社区-FPGA CPLD-ChipDebug](https://chipdebug.com/wp-content/uploads/2022/08/a681252a5f223945.png)
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